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([2a0a:f640:1501:b1db:c5c6:e8a1:c6ef:dac9]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b3128506sm947524066b.28.2025.09.15.06.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 06:23:47 -0700 (PDT) Message-ID: <8d3396b17fddc8f192c12878b6d01cff8ec7af76.camel@gmail.com> Subject: Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits From: timur.kristof@gmail.com To: Alex Deucher Cc: Alex Deucher , amd-gfx@lists.freedesktop.org, christian.koenig@amd.com Date: Mon, 15 Sep 2025 15:23:45 +0200 In-Reply-To: References: <20250911172449.3340848-1-alexander.deucher@amd.com> <20250911172449.3340848-3-alexander.deucher@amd.com> <8acbb3b27a933b60b17b06a03454cc171f1cefc8.camel@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Mon, 2025-09-15 at 09:07 -0400, Alex Deucher wrote: > On Sat, Sep 13, 2025 at 1:28=E2=80=AFAM wrote: > >=20 > > On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote: > > > On Thu, Sep 11, 2025 at 2:18=E2=80=AFPM Alex Deucher > > > > > > wrote: > > > >=20 > > > > On Thu, Sep 11, 2025 at 1:25=E2=80=AFPM Alex Deucher > > > > wrote: > > > > >=20 > > > > > SDMA 5.2.x has increased transfer limits. > > > > >=20 > > > > > v2: fix harder, use shifts to make it more obvious > > > > >=20 > > > > > Signed-off-by: Alex Deucher > > > > > --- > > > > > =C2=A0drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- > > > > > =C2=A01 file changed, 2 insertions(+), 2 deletions(-) > > > > >=20 > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > > > index a8e39df29f343..bf227eadbe487 100644 > > > > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > > > @@ -2065,11 +2065,11 @@ static void > > > > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, > > > > > =C2=A0} > > > > >=20 > > > > > =C2=A0static const struct amdgpu_buffer_funcs > > > > > sdma_v5_2_buffer_funcs =3D > > > > > { > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .copy_max_bytes =3D 0x40000= 0, > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .copy_max_bytes =3D 1 << 30= , > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .copy_num_dw =3D 7, > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .emit_copy_buffer =3D = sdma_v5_2_emit_copy_buffer, > > > > >=20 > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .fill_max_bytes =3D 0x40000= 0, > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .fill_max_bytes =3D 1 << 30= , > > > >=20 > > > > The hw docs and PAL differ here.=C2=A0 I've asked the hw designers > > > > to > > > > clarify. > > >=20 > > > The HW team verified that the hardware supports the extended > > > range > > > for > > > both copies and fills. > > >=20 > > > Alex > >=20 > > Hi Alex, > >=20 > > This is still pretty confusing. > > According to PAL, only SDMA v6 has the extended range for fills, > > and it > > can do 4 bytes fewer. > >=20 > > Are you sure that PAL is wrong about this? >=20 > I can talk to the PAL team as well.=C2=A0 I talked to the hardware > designers and they verified that the hardware has the higher limit. > It's the same underlying hardware so it makes sense that both copies > and fills would have the same limit. I am worried that they found some issues with it and that's why they didn't enable it. >=20 > >=20 > > For reference: > > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/= gfx10/gfx10DmaCmdBuffer.cpp > > https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/= gfx12/gfx12DmaCmdBuffer.cpp > >=20 > > MaxCopySize on GFX10: 1 << 22 > > MaxCopySize on GFX10.3+: 1 << 30 > >=20 > > MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3 > > MaxFillSize on GFX11+: (1 << 30 - 1) & ~3 > > This makes sense because they program the count field in the packet > > using the byte count minus four. >=20 > They are setting up the packet for dword fill rather than byte fill > so > count becomes dword aligned: >=20 > =C2=A0=C2=A0=C2=A0 // Because we will set fillsize =3D 2, the low two bit= s of our > "count" are ignored, but we still program > =C2=A0=C2=A0=C2=A0 // this in terms of bytes. Yes. I thought we would prefer to use dword fill in the kernel as well, isn't that the case? I thought dword fill is faster and everything that the kernel fills would be already dword aligned. Am I missing something? Thanks, Timur