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Wed, 29 Oct 2025 11:41:11 +0000 Message-ID: <8d716ca2-43d3-4c69-8d6a-e270c357c44d@amd.com> Date: Wed, 29 Oct 2025 12:41:07 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 11/14] drm/amdgpu/vce1: Ensure VCPU BO is in lower 32-bit address space To: =?UTF-8?Q?Timur_Krist=C3=B3f?= , amd-gfx@lists.freedesktop.org, Alex Deucher , Alexandre Demers , Rodrigo Siqueira References: <20251028220628.8371-1-timur.kristof@gmail.com> <20251028220628.8371-12-timur.kristof@gmail.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20251028220628.8371-12-timur.kristof@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR2P281CA0063.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:93::19) To PH7PR12MB5685.namprd12.prod.outlook.com (2603:10b6:510:13c::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB5685:EE_|SJ1PR12MB6145:EE_ X-MS-Office365-Filtering-Correlation-Id: fd0458a5-aa6a-41f8-affb-08de16e00f33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|7053199007; 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And we make sure > that the GART is located at the low address range. > That way the VCE1 can access the VCPU BO. > > Signed-off-by: Timur Kristóf > Co-developed-by: Alexandre Demers > Signed-off-by: Alexandre Demers > Co-developed-by: Christian König > Signed-off-by: Christian König Make that a suggested-by and drop co-developed and signed-off-by for me. The code was solely written by you if I'm not completely mistaken. Patch itself is Reviewed-by: Christian König Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 44 +++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > index e62fd8ed1992..27f70146293d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > @@ -34,6 +34,7 @@ > > #include "amdgpu.h" > #include "amdgpu_vce.h" > +#include "amdgpu_gart.h" > #include "sid.h" > #include "vce_v1_0.h" > #include "vce/vce_1_0_d.h" > @@ -46,6 +47,11 @@ > #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) > #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 > > +#define VCE_V1_0_GART_PAGE_START \ > + (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) > +#define VCE_V1_0_GART_ADDR_START \ > + (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) > + > static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); > static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); > > @@ -535,6 +541,38 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) > return 0; > } > > +/** > + * vce_v1_0_ensure_vcpu_bo_32bit_addr() - ensure the VCPU BO has a 32-bit address > + * > + * @adev: amdgpu_device pointer > + * > + * Due to various hardware limitations, the VCE1 requires > + * the VCPU BO to be in the low 32 bit address range. > + * Ensure that the VCPU BO has a 32-bit GPU address, > + * or return an error code when that isn't possible. > + */ > +static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) > +{ > + const u64 gpu_addr = amdgpu_bo_gpu_offset(adev->vce.vcpu_bo); > + const u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); > + const u64 max_vcpu_bo_addr = 0xffffffff - bo_size; > + > + /* Check if the VCPU BO already has a 32-bit address. > + * Eg. if MC is configured to put VRAM in the low address range. > + */ > + if (gpu_addr <= max_vcpu_bo_addr) > + return 0; > + > + /* Check if we can map the VCPU BO in GART to a 32-bit address. */ > + if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) > + return -EINVAL; > + > + amdgpu_gart_bind_vram_bo(adev, VCE_V1_0_GART_ADDR_START, adev->vce.vcpu_bo, > + AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID); > + adev->vce.gpu_addr = adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; > + return 0; > +} > + > static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) > { > struct amdgpu_device *adev = ip_block->adev; > @@ -554,6 +592,9 @@ static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) > if (r) > return r; > r = vce_v1_0_load_fw_signature(adev); > + if (r) > + return r; > + r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); > if (r) > return r; > > @@ -669,6 +710,9 @@ static int vce_v1_0_resume(struct amdgpu_ip_block *ip_block) > if (r) > return r; > r = vce_v1_0_load_fw_signature(adev); > + if (r) > + return r; > + r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); > if (r) > return r; >