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b=IOgmnRtsazJ4bXvL+b1qsNp2p90w67Tj2zVKE2lNxZiqfTkLVpILlH7Tp4AEtIX8IYRn85oCmfMSxpRwbQYp0xfJE0o1SMz+V+vp7Qo0VQEZ/+/ZBc00/RtdCiU2g8xEVPD1w4mUic9Q98v5F/BCgSKhqxlRFWEEibUBMvGRaMA= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DM4PR12MB5040.namprd12.prod.outlook.com (2603:10b6:5:38b::19) by SJ1PR12MB6123.namprd12.prod.outlook.com (2603:10b6:a03:45a::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7698.19; Wed, 19 Jun 2024 07:52:22 +0000 Received: from DM4PR12MB5040.namprd12.prod.outlook.com ([fe80::a3dc:7ea1:9cc7:ce0f]) by DM4PR12MB5040.namprd12.prod.outlook.com ([fe80::a3dc:7ea1:9cc7:ce0f%4]) with mapi id 15.20.7698.019; Wed, 19 Jun 2024 07:52:22 +0000 Message-ID: <8d874e13-f0b7-458b-a514-905df42499d6@amd.com> Date: Wed, 19 Jun 2024 13:22:14 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/7] dmaengine: ae4dma: Register AE4DMA using pt_dmaengine_register To: Philipp Stanner , Basavaraj Natikar , vkoul@kernel.org, dmaengine@vger.kernel.org Cc: Raju.Rangoju@amd.com, Frank.li@nxp.com References: <20240617100359.2550541-1-Basavaraj.Natikar@amd.com> <20240617100359.2550541-6-Basavaraj.Natikar@amd.com> <687174ffdd9eeeefab5309b57bf0001c9d4dae76.camel@redhat.com> Content-Language: en-US From: Basavaraj Natikar In-Reply-To: <687174ffdd9eeeefab5309b57bf0001c9d4dae76.camel@redhat.com> Content-Type: text/plain; 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>> +       int i; >> + >> +       for (i = 0; i < CMD_Q_LEN; i++) >> +               ae4_check_status_error(ae4cmd_q, i); >> +} >> + >>  static void ae4_pending_work(struct work_struct *work) >>  { >>         struct ae4_cmd_queue *ae4cmd_q = container_of(work, struct >> ae4_cmd_queue, p_work.work); >> @@ -123,6 +132,66 @@ static irqreturn_t ae4_core_irq_handler(int irq, >> void *data) >>         return IRQ_HANDLED; >>  } >>   >> +static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct >> ae4_cmd_queue *ae4cmd_q) >> +{ >> +       bool soc = FIELD_GET(DWORD0_SOC, desc->dwouv.dw0); >> +       struct pt_cmd_queue *cmd_q = &ae4cmd_q->cmd_q; >> +       u32 tail_wi; >> + >> +       if (soc) { >> +               desc->dwouv.dw0 |= FIELD_PREP(DWORD0_IOC, desc- >>> dwouv.dw0); >> +               desc->dwouv.dw0 &= ~DWORD0_SOC; >> +       } >> + >> +       mutex_lock(&ae4cmd_q->cmd_lock); >> + >> +       tail_wi = atomic_read(&ae4cmd_q->tail_wi); >> +       memcpy(&cmd_q->qbase[tail_wi], desc, sizeof(struct >> ae4dma_desc)); >> + >> +       atomic64_inc(&ae4cmd_q->q_cmd_count); >> + >> +       tail_wi = (tail_wi + 1) % CMD_Q_LEN; >> + >> +       atomic_set(&ae4cmd_q->tail_wi, tail_wi); >> +       /* Synchronize ordering */ >> +       mb(); >> + >> +       writel(tail_wi, cmd_q->reg_control + 0x10); >> +       /* Synchronize ordering */ >> +       mb(); > Same here as in patch №2, I think writel() and mutex can't change their > relative order. > >> + >> +       mutex_unlock(&ae4cmd_q->cmd_lock); > Same question: can't everything be done by the mutex alone? Sure , I will remove it in all applicable places. Thanks, -- Basavaraj > > > P. > >> + >> +       wake_up(&ae4cmd_q->q_w); >> + >> +       return 0; >> +} >> + >> +int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q, >> +                            struct pt_passthru_engine *pt_engine) >> +{ >> +       struct ae4_cmd_queue *ae4cmd_q = container_of(cmd_q, struct >> ae4_cmd_queue, cmd_q); >> +       struct ae4dma_desc desc; >> + >> +       cmd_q->cmd_error = 0; >> +       cmd_q->total_pt_ops++; >> +       memset(&desc, 0, sizeof(desc)); >> +       desc.dwouv.dws.byte0 = CMD_AE4_DESC_DW0_VAL; >> + >> +       desc.dw1.status = 0; >> +       desc.dw1.err_code = 0; >> +       desc.dw1.desc_id = 0; >> + >> +       desc.length = pt_engine->src_len; >> + >> +       desc.src_lo = upper_32_bits(pt_engine->src_dma); >> +       desc.src_hi = lower_32_bits(pt_engine->src_dma); >> +       desc.dst_lo = upper_32_bits(pt_engine->dst_dma); >> +       desc.dst_hi = lower_32_bits(pt_engine->dst_dma); >> + >> +       return ae4_core_execute_cmd(&desc, ae4cmd_q); >> +} >> + >>  void ae4_destroy_work(struct ae4_device *ae4) >>  { >>         struct ae4_cmd_queue *ae4cmd_q; >> @@ -202,5 +271,9 @@ int ae4_core_init(struct ae4_device *ae4) >>                 init_completion(&ae4cmd_q->cmp); >>         } >>   >> +       ret = pt_dmaengine_register(pt); >> +       if (ret) >> +               ae4_destroy_work(ae4); >> + >>         return ret; >>  } >> diff --git a/drivers/dma/amd/ae4dma/ae4dma-pci.c >> b/drivers/dma/amd/ae4dma/ae4dma-pci.c >> index ddebf0609c4d..5450fa551eea 100644 >> --- a/drivers/dma/amd/ae4dma/ae4dma-pci.c >> +++ b/drivers/dma/amd/ae4dma/ae4dma-pci.c >> @@ -131,6 +131,7 @@ static int ae4_pci_probe(struct pci_dev *pdev, >> const struct pci_device_id *id) >>   >>         pt = &ae4->pt; >>         pt->dev = dev; >> +       pt->ver = AE4_DMA_VERSION; >>   >>         pt->io_regs = pcim_iomap_table(pdev)[0]; >>         if (!pt->io_regs) { >> diff --git a/drivers/dma/amd/ae4dma/ae4dma.h >> b/drivers/dma/amd/ae4dma/ae4dma.h >> index 4e4584e152a1..f1b6dcc1d8c3 100644 >> --- a/drivers/dma/amd/ae4dma/ae4dma.h >> +++ b/drivers/dma/amd/ae4dma/ae4dma.h >> @@ -16,6 +16,7 @@ >>   >>  #define AE4_DESC_COMPLETED             0x3 >>  #define AE4_DMA_VERSION                        4 >> +#define CMD_AE4_DESC_DW0_VAL           2 >>   >>  struct ae4_msix { >>         int msix_count; >> @@ -36,6 +37,7 @@ struct ae4_cmd_queue { >>         atomic64_t done_cnt; >>         atomic64_t q_cmd_count; >>         atomic_t dridx; >> +       atomic_t tail_wi; >>         unsigned int id; >>  }; >>