From: "Nilawar, Badal" <badal.nilawar@intel.com>
To: Karthik Poosa <karthik.poosa@intel.com>,
<intel-xe@lists.freedesktop.org>
Cc: <anshuman.gupta@intel.com>, <riana.tauro@intel.com>,
<ashutosh.dixit@intel.com>, <rodrigo.vivi@intel.com>,
<michael.j.ruhl@intel.com>
Subject: Re: [PATCH v3 4/5] drm/xe/hwmon: Expose powerX_cap_interval
Date: Mon, 5 May 2025 16:12:41 +0530 [thread overview]
Message-ID: <8e848202-84d3-4edf-8e8d-098b8ee1daff@intel.com> (raw)
In-Reply-To: <20250430203607.926585-5-karthik.poosa@intel.com>
On 01-05-2025 02:06, Karthik Poosa wrote:
> Expose powerX_cap_interval to manage burst power limit time window.
>
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Looks good to me.
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 18 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_hwmon.c | 16 +++++++++++++---
> 2 files changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 9dc2ee348aa6..124fa0883924 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -176,3 +176,21 @@ Description: RW. Package burst (PL2) power limit in microwatts.
> limit. Writing values > 0 and <= TDP will enable the power limit.
>
> Only supported for particular Intel Xe graphics platforms.
> +
> +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_cap_interval
> +Date: May 2025
> +KernelVersion: 6.15
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Card burst power limit interval (Tau in PL2/Tau) in
> + milliseconds over which sustained power is averaged.
> +
> + Only supported for particular Intel Xe graphics platforms.
> +
> +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_cap_interval
> +Date: May 2025
> +KernelVersion: 6.15
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Package burst power limit interval (Tau in PL2/Tau) in
> + milliseconds over which sustained power is averaged.
> +
> + Only supported for particular Intel Xe graphics platforms.
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 115758c88175..ada8c15829a3 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -473,7 +473,7 @@ xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *at
> u32 x, y, x_w = 2; /* 2 bits */
> u64 r, tau4, out;
> int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD;
> - u32 power_attr = PL1_HWMON_ATTR;
> + u32 power_attr = (to_sensor_dev_attr(attr)->index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR;
>
> int ret = 0;
>
> @@ -528,7 +528,7 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
> u64 tau4, r, max_win;
> unsigned long val;
> int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD;
> - u32 power_attr = PL1_HWMON_ATTR;
> + u32 power_attr = (to_sensor_dev_attr(attr)->index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR;
> int ret;
>
> ret = kstrtoul(buf, 0, &val);
> @@ -612,10 +612,20 @@ static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
> static SENSOR_DEVICE_ATTR(power2_max_interval, 0664,
> xe_hwmon_power_max_interval_show,
> xe_hwmon_power_max_interval_store, SENSOR_INDEX_PKG_PL1);
> +/* PSYS PL2 */
> +static SENSOR_DEVICE_ATTR(power1_cap_interval, 0664,
> + xe_hwmon_power_max_interval_show,
> + xe_hwmon_power_max_interval_store, SENSOR_INDEX_PSYS_PL2);
> +/* PKG PL2 */
> +static SENSOR_DEVICE_ATTR(power2_cap_interval, 0664,
> + xe_hwmon_power_max_interval_show,
> + xe_hwmon_power_max_interval_store, SENSOR_INDEX_PKG_PL2);
>
> static struct attribute *hwmon_attributes[] = {
> &sensor_dev_attr_power1_max_interval.dev_attr.attr,
> &sensor_dev_attr_power2_max_interval.dev_attr.attr,
> + &sensor_dev_attr_power1_cap_interval.dev_attr.attr,
> + &sensor_dev_attr_power2_cap_interval.dev_attr.attr,
> NULL
> };
>
> @@ -626,7 +636,7 @@ static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
> struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> int ret = 0;
> int channel = (index % 2) ? CHANNEL_PKG : CHANNEL_CARD;
> - u32 power_attr = PL1_HWMON_ATTR;
> + u32 power_attr = (index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR;
> u32 uval;
>
> xe_pm_runtime_get(hwmon->xe);
next prev parent reply other threads:[~2025-05-05 10:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-30 20:36 [PATCH v3 0/5] drm/xe/hwmon: Add mailbox power limits, PL2, read energy from PMT Karthik Poosa
2025-04-30 20:36 ` [PATCH v3 1/5] drm/xe/hwmon: Add support to manage power limits though mailbox Karthik Poosa
2025-05-02 15:02 ` Nilawar, Badal
2025-05-05 14:02 ` Poosa, Karthik
2025-04-30 20:36 ` [PATCH v3 2/5] drm/xe/hwmon: Move card reactive critical power under channel card Karthik Poosa
2025-04-30 20:36 ` [PATCH v3 3/5] drm/xe/hwmon: Add support to manage PL2 though mailbox Karthik Poosa
2025-05-05 10:41 ` Nilawar, Badal
2025-04-30 20:36 ` [PATCH v3 4/5] drm/xe/hwmon: Expose powerX_cap_interval Karthik Poosa
2025-05-05 10:42 ` Nilawar, Badal [this message]
2025-04-30 20:36 ` [PATCH v3 5/5] drm/xe/hwmon: Read energy status from PMT Karthik Poosa
2025-05-06 7:26 ` Nilawar, Badal
2025-04-30 20:44 ` ✓ CI.Patch_applied: success for drm/xe/hwmon: Add mailbox power limits, PL2, read energy " Patchwork
2025-04-30 20:44 ` ✓ CI.checkpatch: " Patchwork
2025-04-30 20:46 ` ✓ CI.KUnit: " Patchwork
2025-04-30 20:54 ` ✓ CI.Build: " Patchwork
2025-04-30 20:56 ` ✗ CI.Hooks: failure " Patchwork
2025-04-30 20:58 ` ✓ CI.checksparse: success " Patchwork
2025-05-01 9:09 ` ✗ Xe.CI.Full: failure " Patchwork
2025-05-06 7:56 ` ✗ Xe.CI.BAT: " Patchwork
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