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Thu, 07 Mar 2024 03:11:02 -0800 (PST) Message-ID: <8ef64462-d810-4be1-923f-973de340cda2@suse.com> Date: Thu, 7 Mar 2024 12:11:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 11/23] xen/riscv: introduce cmpxchg.h To: Oleksii Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Julien Grall , Stefano Stabellini , Wei Liu , xen-devel@lists.xenproject.org References: <23ff1c20-91f3-4c60-9562-7f1cd57c1043@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 07.03.2024 12:01, Oleksii wrote: > On Thu, 2024-03-07 at 11:46 +0100, Jan Beulich wrote: >> On 07.03.2024 11:35, Oleksii wrote: >>> On Wed, 2024-03-06 at 15:56 +0100, Jan Beulich wrote: >>>> On 26.02.2024 18:38, Oleksii Kurochko wrote: >>>>> The header was taken from Linux kernl 6.4.0-rc1. >>>>> >>>>> Addionally, were updated: >>>>> * add emulation of {cmp}xchg for 1/2 byte types using 32-bit >>>>> atomic >>>>>   access. >>>>> * replace tabs with spaces >>>>> * replace __* variale with *__ >>>>> * introduce generic version of xchg_* and cmpxchg_*. >>>>> >>>>> Implementation of 4- and 8-byte cases were left as it is done >>>>> in >>>>> Linux kernel as according to the RISC-V spec: >>>>> ``` >>>>> Table A.5 ( only part of the table was copied here ) >>>>> >>>>> Linux Construct       RVWMO Mapping >>>>> atomic relaxed    amo.{w|d} >>>>> atomic acquire    amo.{w|d}.aq >>>>> atomic release    amo.{w|d}.rl >>>>> atomic             amo.{w|d}.aqrl >>>>> >>>>> Linux Construct       RVWMO LR/SC Mapping >>>>> atomic relaxed    loop: lr.{w|d}; ; sc.{w|d}; bnez >>>>> loop >>>>> atomic acquire    loop: lr.{w|d}.aq; ; sc.{w|d}; bnez >>>>> loop >>>>> atomic release    loop: lr.{w|d}; ; sc.{w|d}.aqrl∗ ; >>>>> bnez >>>>> loop OR >>>>>                        fence.tso; loop: lr.{w|d}; ; >>>>> sc.{w|d}∗ ; >>>>> bnez loop >>>>> atomic             loop: lr.{w|d}.aq; ; sc.{w|d}.aqrl; >>>>> bnez >>>>> loop Note the load and store forms mentioned here. How would ... >>>>> The Linux mappings for release operations may seem stronger >>>>> than >>>>> necessary, >>>>> but these mappings are needed to cover some cases in which >>>>> Linux >>>>> requires >>>>> stronger orderings than the more intuitive mappings would >>>>> provide. >>>>> In particular, as of the time this text is being written, Linux >>>>> is >>>>> actively >>>>> debating whether to require load-load, load-store, and store- >>>>> store >>>>> orderings >>>>> between accesses in one critical section and accesses in a >>>>> subsequent critical >>>>> section in the same hart and protected by the same >>>>> synchronization >>>>> object. >>>>> Not all combinations of FENCE RW,W/FENCE R,RW mappings with >>>>> aq/rl >>>>> mappings >>>>> combine to provide such orderings. >>>>> There are a few ways around this problem, including: >>>>> 1. Always use FENCE RW,W/FENCE R,RW, and never use aq/rl. This >>>>> suffices >>>>>    but is undesirable, as it defeats the purpose of the aq/rl >>>>> modifiers. >>>>> 2. Always use aq/rl, and never use FENCE RW,W/FENCE R,RW. This >>>>> does >>>>> not >>>>>    currently work due to the lack of load and store opcodes >>>>> with aq >>>>> and rl >>>>>    modifiers. >>>> >>>> As before I don't understand this point. Can you give an example >>>> of >>>> what >>>> sort of opcode / instruction is missing? >>> If I understand the spec correctly then l{b|h|w|d} and s{b|h|w|d} >>> instructions don't have aq or rl annotation. >> >> How would load insns other that LR and store insns other than SC come >> into play here? > > This part of the spec. is not only about LR and SC which cover Load- > Exclusive and Store-Exclusive cases, but also about non-Exclusive cases > for each l{b|h|w|d} and s{b|h|w|d} are used. ... the spec (obviously covering other forms, too) be relevant when reasoning whether just suffixes or actual barrier insns need using? Jan