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Tue, 25 Feb 2020 17:00:25 +0000 MIME-Version: 1.0 Date: Tue, 25 Feb 2020 17:00:24 +0000 From: Marc Zyngier To: Robert Richter Subject: Re: ARM64_SW_TTBR0_PAN enabled causing hangs on OcteonTX In-Reply-To: <20200225163507.3ob4k3wzek5gypis@rric.localdomain> References: <6f3ce71073f38fbd4e0f7b75852a8846@kernel.org> <20200225163507.3ob4k3wzek5gypis@rric.localdomain> Message-ID: <8f2efa884c7cb642a9b9fa66c7949607@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: rrichter@marvell.com, tharvey@gateworks.com, linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, sgoutham@marvell.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200225_090029_554313_BFA8F0B4 X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , Tim Harvey , Will Deacon , Sunil Goutham , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-02-25 16:35, Robert Richter wrote: > Marc, > > On 25.02.20 16:27:41, Marc Zyngier wrote: >> On 2020-02-25 16:13, Tim Harvey wrote: > >> > That does enable the erratum, disable KPTI and boot properly but I >> > misread the erratum and it shouldn't be needed for T81 pass 1.2... the >> > erratum is documented only needed for pass 1.0. >> >> Can you then remove the patch *and* disable KPTI? >> >> TX1 is broken beyond recognition and KPTI is known to explode on this >> HW >> (which is why we disable KPTI on it). We always attributed it to this >> erratum, >> but in the absence of any help from Cavium to identify the problem, we >> just >> keyed it on that. >> >> *IF* this HW is indeed unaffected by it, then it is probably the mix >> of >> KPTI and SWPAN that triggers the issue. If my suspicion is correct, >> you'll >> need to have a chat with Cavium/Marvell to understand what is >> happening >> there. > > I checked the docs and Tim is right, this should be only visible on > pass 1.0. Thus, the rev range to enable the workaround as implemented > upstream should be ok. I have asked hw folks regarding this. Then it could well be that our disabling of KPTI on TX1 is keyed on the wrong erratum. In the absence of a clear explanation of what is going on, we made an educated guess. If oyu're going to find out about what breaks this CPU, it'd be good to understand whether this is the same problem that affects all the other revisions. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel