From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A75EC433FE for ; Mon, 3 Oct 2022 09:43:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229978AbiJCJn0 (ORCPT ); Mon, 3 Oct 2022 05:43:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229953AbiJCJm4 (ORCPT ); Mon, 3 Oct 2022 05:42:56 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E8A385E647; Mon, 3 Oct 2022 02:37:33 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 233C513D5; Mon, 3 Oct 2022 02:37:36 -0700 (PDT) Received: from [10.57.65.226] (unknown [10.57.65.226]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B28833F792; Mon, 3 Oct 2022 02:37:27 -0700 (PDT) Message-ID: <8f865045-aa95-46b6-a455-c3d9c6d26494@arm.com> Date: Mon, 3 Oct 2022 10:37:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v3 04/13] coresight: etm4x: Update ETM4 driver to use Trace ID API From: Suzuki K Poulose To: Mike Leach , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com References: <20220809223401.24599-1-mike.leach@linaro.org> <20220809223401.24599-5-mike.leach@linaro.org> <01570ba2-81c9-e4b5-6669-0e4087a4bd1f@arm.com> In-Reply-To: <01570ba2-81c9-e4b5-6669-0e4087a4bd1f@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On 03/10/2022 10:31, Suzuki K Poulose wrote: > On 09/08/2022 23:33, Mike Leach wrote: >> The trace ID API is now used to allocate trace IDs for ETM4.x / ETE >> devices. >> >> For perf sessions, these will be allocated on enable, and released on >> disable. >> >> For sysfs sessions, these will be allocated on enable, but only released >> on reset. This allows the sysfs session to interrogate the Trace ID used >> after the session is over - maintaining functional consistency with the >> previous allocation scheme. >> >> The trace ID will also be allocated on read of the mgmt/trctraceid file. >> This ensures that if perf or sysfs read this before enabling trace, the >> value will be the one used for the trace session. >> >> Trace ID initialisation is removed from the _probe() function. >> >> Signed-off-by: Mike Leach >> --- >>   .../coresight/coresight-etm4x-core.c          | 79 +++++++++++++++++-- >>   .../coresight/coresight-etm4x-sysfs.c         | 27 ++++++- >>   drivers/hwtracing/coresight/coresight-etm4x.h |  3 + >>   3 files changed, 100 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index cf249ecad5a5..b4fb28ce89fd 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -42,6 +42,7 @@ >>   #include "coresight-etm4x-cfg.h" >>   #include "coresight-self-hosted-trace.h" >>   #include "coresight-syscfg.h" >> +#include "coresight-trace-id.h" >>   static int boot_enable; >>   module_param(boot_enable, int, 0444); >> @@ -234,6 +235,50 @@ static int etm4_trace_id(struct coresight_device >> *csdev) >>       return drvdata->trcid; >>   } >> +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) >> +{ >> +    int trace_id; >> + >> +    /* >> +     * This will allocate a trace ID to the cpu, >> +     * or return the one currently allocated. >> +     */ >> +    /* trace id function has its own lock */ >> +    trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); >> +    if (IS_VALID_ID(trace_id)) >> +        drvdata->trcid = (u8)trace_id; >> +    else >> +        dev_err(&drvdata->csdev->dev, >> +            "Failed to allocate trace ID for %s on CPU%d\n", >> +            dev_name(&drvdata->csdev->dev), drvdata->cpu); >> +    return trace_id; >> +} >> + >> +static int etm4_set_current_trace_id(struct etmv4_drvdata *drvdata) >> +{ >> +    int trace_id; >> + >> +    /* >> +     * Set the currently allocated trace ID - perf allocates IDs >> +     * as part of setup_aux for all CPUs it may use. >> +     */ >> +    trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); >> +    if (IS_VALID_ID(trace_id)) { >> +        drvdata->trcid = (u8)trace_id; >> +        return 0; >> +    } >> + >> +    dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on >> CPU%d\n", >> +        dev_name(&drvdata->csdev->dev), drvdata->cpu); >> + >> +    return -EINVAL; >> +} > > >> + >> +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) >> +{ >> +    coresight_trace_id_put_cpu_id(drvdata->cpu); >> +} >> + >>   struct etm4_enable_arg { >>       struct etmv4_drvdata *drvdata; >>       int rc; >> @@ -729,6 +774,15 @@ static int etm4_enable_perf(struct >> coresight_device *csdev, >>       ret = etm4_parse_event_config(csdev, event); >>       if (ret) >>           goto out; >> + >> +    /* >> +     * perf allocates cpu ids as part of setup - device needs to use >> +     * the allocated ID. >> +     */ >> +    ret = etm4_set_current_trace_id(drvdata); > > So, when do we allocate an id in perf mode ? As far as I can see, this > should be the same as etm4_read_alloc_trace_id() ? Why are they any > different ? > >> +    if (ret < 0) >> +        goto out; >> + >>       /* And enable it */ >>       ret = etm4_enable_hw(drvdata); >> @@ -753,6 +807,11 @@ static int etm4_enable_sysfs(struct >> coresight_device *csdev) >>       spin_lock(&drvdata->spinlock); >> +    /* sysfs needs to read and allocate a trace ID */ >> +    ret = etm4_read_alloc_trace_id(drvdata); >> +    if (ret < 0) >> +        goto unlock_sysfs_enable; >> + >>       /* >>        * Executing etm4_enable_hw on the cpu whose ETM is being enabled >>        * ensures that register writes occur when cpu is powered. >> @@ -764,6 +823,11 @@ static int etm4_enable_sysfs(struct >> coresight_device *csdev) >>           ret = arg.rc; >>       if (!ret) >>           drvdata->sticky_enable = true; >> + >> +    if (ret) >> +        etm4_release_trace_id(drvdata); >> + >> +unlock_sysfs_enable: >>       spin_unlock(&drvdata->spinlock); >>       if (!ret) >> @@ -895,6 +959,8 @@ static int etm4_disable_perf(struct >> coresight_device *csdev, >>       /* TRCVICTLR::SSSTATUS, bit[9] */ >>       filters->ssstatus = (control & BIT(9)); >> +    /* The perf event will release trace ids when it is destroyed */ >> + > > At this patch level, there is no release of trace id ? Is that missed in > this patch ? Or am I missing something ? I think the above change only comes in PATCH 7. May be that patch needs to be rearranged in order ? Otherwise git-bisect can break running a perf session on cs_etm, with missing traceid. Suzuki From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82441C433F5 for ; Mon, 3 Oct 2022 09:38:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:References:Cc:To:From:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EzeaS+77t7v9Yuua8CpD5AbqBHZI15KbrOvudpL3ezg=; b=vmn5cgVnOyjIo+ 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(Postfix) with ESMTPSA id B28833F792; Mon, 3 Oct 2022 02:37:27 -0700 (PDT) Message-ID: <8f865045-aa95-46b6-a455-c3d9c6d26494@arm.com> Date: Mon, 3 Oct 2022 10:37:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v3 04/13] coresight: etm4x: Update ETM4 driver to use Trace ID API From: Suzuki K Poulose To: Mike Leach , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com References: <20220809223401.24599-1-mike.leach@linaro.org> <20220809223401.24599-5-mike.leach@linaro.org> <01570ba2-81c9-e4b5-6669-0e4087a4bd1f@arm.com> In-Reply-To: <01570ba2-81c9-e4b5-6669-0e4087a4bd1f@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: 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cmFjZSBJRCB1c2VkCj4+IGFmdGVyIHRoZSBzZXNzaW9uIGlzIG92ZXIgLSBtYWludGFpbmluZyBm dW5jdGlvbmFsIGNvbnNpc3RlbmN5IHdpdGggdGhlCj4+IHByZXZpb3VzIGFsbG9jYXRpb24gc2No ZW1lLgo+Pgo+PiBUaGUgdHJhY2UgSUQgd2lsbCBhbHNvIGJlIGFsbG9jYXRlZCBvbiByZWFkIG9m IHRoZSBtZ210L3RyY3RyYWNlaWQgZmlsZS4KPj4gVGhpcyBlbnN1cmVzIHRoYXQgaWYgcGVyZiBv ciBzeXNmcyByZWFkIHRoaXMgYmVmb3JlIGVuYWJsaW5nIHRyYWNlLCB0aGUKPj4gdmFsdWUgd2ls bCBiZSB0aGUgb25lIHVzZWQgZm9yIHRoZSB0cmFjZSBzZXNzaW9uLgo+Pgo+PiBUcmFjZSBJRCBp bml0aWFsaXNhdGlvbiBpcyByZW1vdmVkIGZyb20gdGhlIF9wcm9iZSgpIGZ1bmN0aW9uLgo+Pgo+ PiBTaWduZWQtb2ZmLWJ5OiBNaWtlIExlYWNoIDxtaWtlLmxlYWNoQGxpbmFyby5vcmc+Cj4+IC0t LQo+PiDCoCAuLi4vY29yZXNpZ2h0L2NvcmVzaWdodC1ldG00eC1jb3JlLmPCoMKgwqDCoMKgwqDC oMKgwqAgfCA3OSArKysrKysrKysrKysrKysrKy0tCj4+IMKgIC4uLi9jb3Jlc2lnaHQvY29yZXNp Z2h0LWV0bTR4LXN5c2ZzLmPCoMKgwqDCoMKgwqDCoMKgIHwgMjcgKysrKysrLQo+PiDCoCBkcml2 ZXJzL2h3dHJhY2luZy9jb3Jlc2lnaHQvY29yZXNpZ2h0LWV0bTR4LmggfMKgIDMgKwo+PiDCoCAz IGZpbGVzIGNoYW5nZWQsIDEwMCBpbnNlcnRpb25zKCspLCA5IGRlbGV0aW9ucygtKQo+Pgo+PiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9od3RyYWNpbmcvY29yZXNpZ2h0L2NvcmVzaWdodC1ldG00eC1j b3JlLmMgCj4+IGIvZHJpdmVycy9od3RyYWNpbmcvY29yZXNpZ2h0L2NvcmVzaWdodC1ldG00eC1j b3JlLmMKPj4gaW5kZXggY2YyNDllY2FkNWE1Li5iNGZiMjhjZTg5ZmQgMTAwNjQ0Cj4+IC0tLSBh L2RyaXZlcnMvaHd0cmFjaW5nL2NvcmVzaWdodC9jb3Jlc2lnaHQtZXRtNHgtY29yZS5jCj4+ICsr KyBiL2RyaXZlcnMvaHd0cmFjaW5nL2NvcmVzaWdodC9jb3Jlc2lnaHQtZXRtNHgtY29yZS5jCj4+ IEBAIC00Miw2ICs0Miw3IEBACj4+IMKgICNpbmNsdWRlICJjb3Jlc2lnaHQtZXRtNHgtY2ZnLmgi Cj4+IMKgICNpbmNsdWRlICJjb3Jlc2lnaHQtc2VsZi1ob3N0ZWQtdHJhY2UuaCIKPj4gwqAgI2lu Y2x1ZGUgImNvcmVzaWdodC1zeXNjZmcuaCIKPj4gKyNpbmNsdWRlICJjb3Jlc2lnaHQtdHJhY2Ut aWQuaCIKPj4gwqAgc3RhdGljIGludCBib290X2VuYWJsZTsKPj4gwqAgbW9kdWxlX3BhcmFtKGJv b3RfZW5hYmxlLCBpbnQsIDA0NDQpOwo+PiBAQCAtMjM0LDYgKzIzNSw1MCBAQCBzdGF0aWMgaW50 IGV0bTRfdHJhY2VfaWQoc3RydWN0IGNvcmVzaWdodF9kZXZpY2UgCj4+ICpjc2RldikKPj4gwqDC oMKgwqDCoCByZXR1cm4gZHJ2ZGF0YS0+dHJjaWQ7Cj4+IMKgIH0KPj4gK2ludCBldG00X3JlYWRf YWxsb2NfdHJhY2VfaWQoc3RydWN0IGV0bXY0X2RydmRhdGEgKmRydmRhdGEpCj4+ICt7Cj4+ICvC oMKgwqAgaW50IHRyYWNlX2lkOwo+PiArCj4+ICvCoMKgwqAgLyoKPj4gK8KgwqDCoMKgICogVGhp cyB3aWxsIGFsbG9jYXRlIGEgdHJhY2UgSUQgdG8gdGhlIGNwdSwKPj4gK8KgwqDCoMKgICogb3Ig cmV0dXJuIHRoZSBvbmUgY3VycmVudGx5IGFsbG9jYXRlZC4KPj4gK8KgwqDCoMKgICovCj4+ICvC oMKgwqAgLyogdHJhY2UgaWQgZnVuY3Rpb24gaGFzIGl0cyBvd24gbG9jayAqLwo+PiArwqDCoMKg IHRyYWNlX2lkID0gY29yZXNpZ2h0X3RyYWNlX2lkX2dldF9jcHVfaWQoZHJ2ZGF0YS0+Y3B1KTsK Pj4gK8KgwqDCoCBpZiAoSVNfVkFMSURfSUQodHJhY2VfaWQpKQo+PiArwqDCoMKgwqDCoMKgwqAg ZHJ2ZGF0YS0+dHJjaWQgPSAodTgpdHJhY2VfaWQ7Cj4+ICvCoMKgwqAgZWxzZQo+PiArwqDCoMKg wqDCoMKgwqAgZGV2X2VycigmZHJ2ZGF0YS0+Y3NkZXYtPmRldiwKPj4gK8KgwqDCoMKgwqDCoMKg wqDCoMKgwqAgIkZhaWxlZCB0byBhbGxvY2F0ZSB0cmFjZSBJRCBmb3IgJXMgb24gQ1BVJWRcbiIs Cj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGRldl9uYW1lKCZkcnZkYXRhLT5jc2Rldi0+ZGV2 KSwgZHJ2ZGF0YS0+Y3B1KTsKPj4gK8KgwqDCoCByZXR1cm4gdHJhY2VfaWQ7Cj4+ICt9Cj4+ICsK Pj4gK3N0YXRpYyBpbnQgZXRtNF9zZXRfY3VycmVudF90cmFjZV9pZChzdHJ1Y3QgZXRtdjRfZHJ2 ZGF0YSAqZHJ2ZGF0YSkKPj4gK3sKPj4gK8KgwqDCoCBpbnQgdHJhY2VfaWQ7Cj4+ICsKPj4gK8Kg wqDCoCAvKgo+PiArwqDCoMKgwqAgKiBTZXQgdGhlIGN1cnJlbnRseSBhbGxvY2F0ZWQgdHJhY2Ug SUQgLSBwZXJmIGFsbG9jYXRlcyBJRHMKPj4gK8KgwqDCoMKgICogYXMgcGFydCBvZiBzZXR1cF9h dXggZm9yIGFsbCBDUFVzIGl0IG1heSB1c2UuCj4+ICvCoMKgwqDCoCAqLwo+PiArwqDCoMKgIHRy YWNlX2lkID0gY29yZXNpZ2h0X3RyYWNlX2lkX3JlYWRfY3B1X2lkKGRydmRhdGEtPmNwdSk7Cj4+ ICvCoMKgwqAgaWYgKElTX1ZBTElEX0lEKHRyYWNlX2lkKSkgewo+PiArwqDCoMKgwqDCoMKgwqAg ZHJ2ZGF0YS0+dHJjaWQgPSAodTgpdHJhY2VfaWQ7Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4g MDsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBkZXZfZXJyKCZkcnZkYXRhLT5jc2Rldi0+ ZGV2LCAiRmFpbGVkIHRvIHNldCB0cmFjZSBJRCBmb3IgJXMgb24gCj4+IENQVSVkXG4iLAo+PiAr wqDCoMKgwqDCoMKgwqAgZGV2X25hbWUoJmRydmRhdGEtPmNzZGV2LT5kZXYpLCBkcnZkYXRhLT5j cHUpOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIC1FSU5WQUw7Cj4+ICt9Cj4gCj4gCj4+ICsKPj4g K3ZvaWQgZXRtNF9yZWxlYXNlX3RyYWNlX2lkKHN0cnVjdCBldG12NF9kcnZkYXRhICpkcnZkYXRh KQo+PiArewo+PiArwqDCoMKgIGNvcmVzaWdodF90cmFjZV9pZF9wdXRfY3B1X2lkKGRydmRhdGEt PmNwdSk7Cj4+ICt9Cj4+ICsKPj4gwqAgc3RydWN0IGV0bTRfZW5hYmxlX2FyZyB7Cj4+IMKgwqDC oMKgwqAgc3RydWN0IGV0bXY0X2RydmRhdGEgKmRydmRhdGE7Cj4+IMKgwqDCoMKgwqAgaW50IHJj Owo+PiBAQCAtNzI5LDYgKzc3NCwxNSBAQCBzdGF0aWMgaW50IGV0bTRfZW5hYmxlX3BlcmYoc3Ry dWN0IAo+PiBjb3Jlc2lnaHRfZGV2aWNlICpjc2RldiwKPj4gwqDCoMKgwqDCoCByZXQgPSBldG00 X3BhcnNlX2V2ZW50X2NvbmZpZyhjc2RldiwgZXZlbnQpOwo+PiDCoMKgwqDCoMKgIGlmIChyZXQp Cj4+IMKgwqDCoMKgwqDCoMKgwqDCoCBnb3RvIG91dDsKPj4gKwo+PiArwqDCoMKgIC8qCj4+ICvC oMKgwqDCoCAqIHBlcmYgYWxsb2NhdGVzIGNwdSBpZHMgYXMgcGFydCBvZiBzZXR1cCAtIGRldmlj ZSBuZWVkcyB0byB1c2UKPj4gK8KgwqDCoMKgICogdGhlIGFsbG9jYXRlZCBJRC4KPj4gK8KgwqDC oMKgICovCj4+ICvCoMKgwqAgcmV0ID0gZXRtNF9zZXRfY3VycmVudF90cmFjZV9pZChkcnZkYXRh KTsKPiAKPiBTbywgd2hlbiBkbyB3ZSBhbGxvY2F0ZSBhbiBpZCBpbiBwZXJmIG1vZGUgPyBBcyBm YXIgYXMgSSBjYW4gc2VlLCB0aGlzCj4gc2hvdWxkIGJlIHRoZSBzYW1lIGFzIGV0bTRfcmVhZF9h bGxvY190cmFjZV9pZCgpID8gV2h5IGFyZSB0aGV5IGFueQo+IGRpZmZlcmVudCA/Cj4gCj4+ICvC oMKgwqAgaWYgKHJldCA8IDApCj4+ICvCoMKgwqDCoMKgwqDCoCBnb3RvIG91dDsKPj4gKwo+PiDC oMKgwqDCoMKgIC8qIEFuZCBlbmFibGUgaXQgKi8KPj4gwqDCoMKgwqDCoCByZXQgPSBldG00X2Vu YWJsZV9odyhkcnZkYXRhKTsKPj4gQEAgLTc1Myw2ICs4MDcsMTEgQEAgc3RhdGljIGludCBldG00 X2VuYWJsZV9zeXNmcyhzdHJ1Y3QgCj4+IGNvcmVzaWdodF9kZXZpY2UgKmNzZGV2KQo+PiDCoMKg wqDCoMKgIHNwaW5fbG9jaygmZHJ2ZGF0YS0+c3BpbmxvY2spOwo+PiArwqDCoMKgIC8qIHN5c2Zz IG5lZWRzIHRvIHJlYWQgYW5kIGFsbG9jYXRlIGEgdHJhY2UgSUQgKi8KPj4gK8KgwqDCoCByZXQg PSBldG00X3JlYWRfYWxsb2NfdHJhY2VfaWQoZHJ2ZGF0YSk7Cj4+ICvCoMKgwqAgaWYgKHJldCA8 IDApCj4+ICvCoMKgwqDCoMKgwqDCoCBnb3RvIHVubG9ja19zeXNmc19lbmFibGU7Cj4+ICsKPj4g wqDCoMKgwqDCoCAvKgo+PiDCoMKgwqDCoMKgwqAgKiBFeGVjdXRpbmcgZXRtNF9lbmFibGVfaHcg b24gdGhlIGNwdSB3aG9zZSBFVE0gaXMgYmVpbmcgZW5hYmxlZAo+PiDCoMKgwqDCoMKgwqAgKiBl bnN1cmVzIHRoYXQgcmVnaXN0ZXIgd3JpdGVzIG9jY3VyIHdoZW4gY3B1IGlzIHBvd2VyZWQuCj4+ IEBAIC03NjQsNiArODIzLDExIEBAIHN0YXRpYyBpbnQgZXRtNF9lbmFibGVfc3lzZnMoc3RydWN0 IAo+PiBjb3Jlc2lnaHRfZGV2aWNlICpjc2RldikKPj4gwqDCoMKgwqDCoMKgwqDCoMKgIHJldCA9 IGFyZy5yYzsKPj4gwqDCoMKgwqDCoCBpZiAoIXJldCkKPj4gwqDCoMKgwqDCoMKgwqDCoMKgIGRy dmRhdGEtPnN0aWNreV9lbmFibGUgPSB0cnVlOwo+PiArCj4+ICvCoMKgwqAgaWYgKHJldCkKPj4g K8KgwqDCoMKgwqDCoMKgIGV0bTRfcmVsZWFzZV90cmFjZV9pZChkcnZkYXRhKTsKPj4gKwo+PiAr dW5sb2NrX3N5c2ZzX2VuYWJsZToKPj4gwqDCoMKgwqDCoCBzcGluX3VubG9jaygmZHJ2ZGF0YS0+ c3BpbmxvY2spOwo+PiDCoMKgwqDCoMKgIGlmICghcmV0KQo+PiBAQCAtODk1LDYgKzk1OSw4IEBA IHN0YXRpYyBpbnQgZXRtNF9kaXNhYmxlX3BlcmYoc3RydWN0IAo+PiBjb3Jlc2lnaHRfZGV2aWNl ICpjc2RldiwKPj4gwqDCoMKgwqDCoCAvKiBUUkNWSUNUTFI6OlNTU1RBVFVTLCBiaXRbOV0gKi8K Pj4gwqDCoMKgwqDCoCBmaWx0ZXJzLT5zc3N0YXR1cyA9IChjb250cm9sICYgQklUKDkpKTsKPj4g K8KgwqDCoCAvKiBUaGUgcGVyZiBldmVudCB3aWxsIHJlbGVhc2UgdHJhY2UgaWRzIHdoZW4gaXQg aXMgZGVzdHJveWVkICovCj4+ICsKPiAKPiBBdCB0aGlzIHBhdGNoIGxldmVsLCB0aGVyZSBpcyBu byByZWxlYXNlIG9mIHRyYWNlIGlkID8gSXMgdGhhdCBtaXNzZWQgaW4KPiB0aGlzIHBhdGNoID8g T3IgYW0gSSBtaXNzaW5nIHNvbWV0aGluZyA/CgpJIHRoaW5rIHRoZSBhYm92ZSBjaGFuZ2Ugb25s eSBjb21lcyBpbiBQQVRDSCA3LiBNYXkgYmUgdGhhdCBwYXRjaCBuZWVkcyAKdG8gYmUgcmVhcnJh bmdlZCBpbiBvcmRlciA/IE90aGVyd2lzZSBnaXQtYmlzZWN0IGNhbiBicmVhayBydW5uaW5nIGEg CnBlcmYgc2Vzc2lvbiBvbiBjc19ldG0sIHdpdGggbWlzc2luZyB0cmFjZWlkLgoKU3V6dWtpCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0t a2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcK aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2Vy bmVsCg==