Re: [RFC v2 6/6] drm/i915/dsc: Check if dsc prefill sufficient for vblank

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 12/17/2024 11:37 PM, Mitul Golani wrote:
> Check if dsc prefill latency is sufficient for vblank.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/skl_watermark.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index a538e2b82c12..0f1ee755fd8a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2292,6 +2292,25 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>   	return 0;
>   }
>   
> +static int
> +skl_dsc_prefill_time(const struct intel_crtc_state *crtc_state)
> +{
> +	const struct intel_crtc_scaler_state *scaler_state =
> +					&crtc_state->scaler_state;
> +	int hscale = scaler_state->scalers[0].hscale;
> +	int vscale = scaler_state->scalers[0].vscale;
> +
> +	if (!crtc_state->dsc.compression_enable)
> +		return 0;
> +	/*
> +	 * FIXME: CDCLK Prefill adjustment to add
> +	 */
> +	if (scaler_state->scaler_users)
> +		return DIV_ROUND_UP(15 * crtc_state->linetime * hscale * vscale, 10);

As mentioned in previous patch, hscale and vscale are left shifted 
values, need to compute this precisely.

Also as per spec for pipe scaler is used for 444 to 420 conversion. 
Chroma subsampling is a 2x downscale. So need to account for it.

Regards,

Ankit

> +
> +	return 0;
> +}
> +
>   static int
>   scaler_prefill_time(const struct intel_crtc_state *crtc_state)
>   {
> @@ -2324,6 +2343,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>   	return crtc_state->framestart_delay +
>   		intel_usecs_to_scanlines(adjusted_mode, latency) +
>   		scaler_prefill_time(crtc_state) +
> +		skl_dsc_prefill_time(crtc_state) +
>   		wm0_lines >
>   		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>   }