From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6920C606A31D for ; Tue, 27 Oct 2026 21:23:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256 header.s=selector1 header.b=NGIBvgsx Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02C0410E474; Tue, 27 Oct 2026 21:23:52 +0000 (UTC) Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013011.outbound.protection.outlook.com [40.107.201.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9A42A10E474 for ; Tue, 27 Oct 2026 21:23:45 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=f3FOQKAX+aYc7D7Rl2EYr+mI+rRPBkdy68U9IcEZidQ3mBNzLITEBf8VIrh3Zf1LwQNhmIRN6xxMRNvJ2sP6ST0rCeVhb9zduA8nIcJR2HntalJoRIUQ+iU47WU+oTYkIkumHp6/HvI01vdbLTofLcdvq8ED8C/3ng1xVA9ZxSiDVw4q6J61sHjwSbQhDrSnU88p2umHMA9mr481V26On6zjEfUOG9CWfwUPHA9UI3jBFT897awcP+z/za2qgqGrx4vGs6kqucXszXs00ObKX3OUXebYfYQIYcdAzynVVO/zLeOk+MEkNwIi9bBYbLwSjNgzkEJB6L4V5lleXjTzxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6vvNU9L3n25+Ya2Z2wduLFB4bXaiAbiGQGsZoJMUoSA=; b=SQF4igICMWPWlQtcwNKWh3BKjdGgycAzYkezU0/SNxZi4jXo6yXf+HpH/hQlZhpFeCjMz4Sp1KwSjxah8wF033H0jn0EZ22S7WM4nWfVdHCcfp/T8vxOC9qp7N8QlOsenLS6BUgROacwNKhthDmSqYw9OUfhHPqdJTwb8UPjGLpOThAB8QQ4gdi0j3GCdUv82G83Fd/blhLya2WNLhHgQezVqhTPsLkWdw12bIvfCwxVVVxLjZtUCCWvteuAHX70/hjCDMy5pp3PmGmUHnRwFMXkbifVda6CTbgUEt2JLmRIssK5ME08oXZQwoaA6oAuUGS62wY0InHC3d20NdBrdg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6vvNU9L3n25+Ya2Z2wduLFB4bXaiAbiGQGsZoJMUoSA=; b=NGIBvgsxGK9M/abx+APQhBhytujx5Ro7PSJ/orT8YecZksVoXt26BUYPCnmVB3/P9OKXNOl00IEZlHsaYsftdw19C3h1WQrTtxhNtfn0CfyRTvZw9Kjoq90oBPIgNaJKDJlr2z0qIVBCxDBAYL7SlxauG3qfb1TMqw4tL8E5U4U= Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BN7PPF5F16C5C9C.namprd12.prod.outlook.com (2603:10b6:40f:fc02::607) by DS7PR12MB6287.namprd12.prod.outlook.com (2603:10b6:8:94::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.22; Tue, 27 Oct 2026 21:23:42 +0000 Received: from BN7PPF5F16C5C9C.namprd12.prod.outlook.com ([fe80::67a7:9feb:71ef:964a]) by BN7PPF5F16C5C9C.namprd12.prod.outlook.com ([fe80::67a7:9feb:71ef:964a%8]) with mapi id 15.21.0546.021; Tue, 27 Oct 2026 21:23:42 +0000 Message-ID: <903e67ef-be21-4131-a5be-7b7ed433b48e@amd.com> Date: Tue, 27 Oct 2026 17:23:40 -0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCHv2 2/8] drm/amdgpu: Support VMID 0 GPUVA completion WB address for UALink To: Mukul Joshi , amd-gfx@lists.freedesktop.org Cc: Harish.Kasiviswanathan@amd.com, philip.yang@amd.com References: <20261027195913.1794477-1-mukul.joshi@amd.com> <20261027195913.1794477-3-mukul.joshi@amd.com> Content-Language: en-US From: Felix Kuehling Organization: AMD Inc. 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So far that has always been an NPA. > > The FW can also take a VMID 0 GPUVA, selected by setting DW4 of the > command to 1. Return the VMID 0 GPUVA of the writeback slot from > amdgpu_ualink_get_wb_addr() alongside the NPA, and use it in > UALink loopback mode. There the HW only carries importer -> exporter > traffic, so the FW cannot write the completion back over NPA. > > Outside loopback the NPA is still used and DW4 stays 0. > > Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 48 +++++++++++++++------- > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c > index 2cd6dc71ab9f..a186859dee3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c > @@ -5641,9 +5641,9 @@ static void amdgpu_ualink_emit_update_wb_addr(u32 **cpu_addr_p, u32 wb_data, > > *cpu_addr++ = cmd; > *cpu_addr++ = wb_data; > - *cpu_addr++ = dw1 & 0xFFFFFFFC; /* lower32 wb_npa */ > - *cpu_addr++ = dw0 & 0xFFFFF; /* upper32 wb_npa */ > - *cpu_addr++ = 0; > + *cpu_addr++ = dw1 & 0xFFFFFFFC; /* lower32 wb address */ > + *cpu_addr++ = dw0 & 0xFFFFF; /* upper32 wb address */ > + *cpu_addr++ = dw2; /* 1: wb address is VMID 0 GPUVA, 0: NPA */ > *cpu_addr++ = 0; > *cpu_addr++ = 0; /* metadata */ > *cpu_addr++ = 0; /* metadata */ > @@ -5857,7 +5857,7 @@ static int amdgpu_ualink_send_command(struct amdgpu_device *adev, > static void amdgpu_ualink_get_wb_addr(struct amdgpu_device *adev, > u32 remote_accel_id, > struct amdgpu_ualink_wb **wb_cpu, > - u64 *wb_npa, u32 type) > + u64 *wb_npa, u64 *wb_gpu, u32 type) > { > struct amdgpu_ualink_remote *remote = to_remote(adev); > /* The GPUID encoded in the write-back NPA address is the routing target > @@ -5870,15 +5870,17 @@ static void amdgpu_ualink_get_wb_addr(struct amdgpu_device *adev, > u32 accel_id = ualink_exp_accel_id(adev); > u32 rb_size = AMDGPU_GPU_PAGE_ALIGN(2 * AMDGPU_UALINK_RB_SIZE); > uintptr_t wb; > - u64 npa; > + u64 gpu, npa; > u32 offset = 0; > > if (ualink_addr_mode(adev) == AMDGPU_UALINK_ADDR_MODE_SOURCE_IDENT) { > wb = (uintptr_t)remote->rb_cpu_addr + rb_size * remote->num_accel; > + gpu = remote->rb_gpu_addr + rb_size * remote->num_accel; > npa = amdgpu_ualink_npa_addr(adev, RB_TYPE_TAILPTR, > remote_accel_id, accel_id); > } else { > wb = (uintptr_t)remote->rptr_cpu_addr; > + gpu = remote->rptr_gpu_addr; > npa = remote->rptr_npa; > npa |= (u64)accel_id << AMDGPU_UALINK_GART_NPA_ADDR_GPUID_SHIFT; > } > @@ -5891,9 +5893,11 @@ static void amdgpu_ualink_get_wb_addr(struct amdgpu_device *adev, > *wb_cpu = (struct amdgpu_ualink_wb *)(wb + offset); > if (wb_npa) > *wb_npa = npa + offset; > + if (wb_gpu) > + *wb_gpu = gpu + offset; > > - dev_dbg(adev->dev, "source %d remote %d wb npa 0x%llx\n", accel_id, > - remote_accel_id, npa + offset); > + dev_dbg(adev->dev, "source %d remote %d wb npa 0x%llx gpu 0x%llx\n", accel_id, > + remote_accel_id, npa + offset, gpu + offset); > } > > struct amdgpu_ualink_wptr_fence_cb { > @@ -6057,9 +6061,9 @@ static int amdgpu_ualink_ring_resync_ptrs(struct amdgpu_device *adev, > ualink_exp_accel_id(adev), peer->interrupt.wptr, peer->shootdown.wptr, > remote_accel_id, int_wptr, tlb_wptr); > > - amdgpu_ualink_get_wb_addr(adev, remote_accel_id, &int_wb, NULL, > + amdgpu_ualink_get_wb_addr(adev, remote_accel_id, &int_wb, NULL, NULL, > RB_TYPE_REMOTE_INTERRUPT); > - amdgpu_ualink_get_wb_addr(adev, remote_accel_id, &tlb_wb, NULL, > + amdgpu_ualink_get_wb_addr(adev, remote_accel_id, &tlb_wb, NULL, NULL, > RB_TYPE_TLB_INV); > > peer->interrupt.wptr = int_wptr; > @@ -6093,7 +6097,8 @@ static int amdgpu_ualink_update_wb_address(struct amdgpu_device *adev, > struct amdgpu_ualink_peer *peer; > struct amdgpu_ualink_ring *ring; > struct amdgpu_ualink_wb *wb_cpu; > - u64 wb_npa; > + u64 wb_npa, wb_gpu, wb_addr; > + u32 wb_vmid0; > int r; > > peer = &remote->peer[remote_accel_id]; > @@ -6105,13 +6110,28 @@ static int amdgpu_ualink_update_wb_address(struct amdgpu_device *adev, > return -EINVAL; > > amdgpu_ualink_get_wb_addr(adev, remote_accel_id, &wb_cpu, &wb_npa, > - ring_type); > + &wb_gpu, ring_type); > + > + /* UALink loopback: HW only carries importer -> exporter traffic, so the > + * MPNHT FW cannot write the completion back over NPA. Hand it the VMID 0 > + * GPUVA of the writeback instead and flag it in DW4 of the command. > + */ > + if (adev->ualink.loopback.enabled) { > + wb_addr = wb_gpu; > + wb_vmid0 = 1; > + } else { > + wb_addr = wb_npa; > + wb_vmid0 = 0; > + } > + > + dev_dbg(adev->dev, "remote %u ring type %u wb %s 0x%llx\n", > + remote_accel_id, ring_type, wb_vmid0 ? "gpuva" : "npa", wb_addr); > > r = amdgpu_ualink_send_command(adev, remote_accel_id, ring, wb_cpu, > amdgpu_ualink_emit_update_wb_addr, > - upper_32_bits(wb_npa), > - lower_32_bits(wb_npa), > - 0, 0); > + upper_32_bits(wb_addr), > + lower_32_bits(wb_addr), > + wb_vmid0, 0); > if (!r) { > ring->wb_cpu = wb_cpu; > ring->ready = true;