From: chandanu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
To: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
hoegsberg-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
jeykumar-jfJNa2p1gH1BDgjK7y7TUQ@public.gmane.org
Subject: Re: [DPU PATCH v2 1/2] drm/msm/dsi: adjust dsi timing for dual dsi mode
Date: Wed, 18 Apr 2018 14:51:34 -0700 [thread overview]
Message-ID: <90a2cb964e14f3d06e901013ab3c1356@codeaurora.org> (raw)
In-Reply-To: <20180417202802.GO73214@art_vandelay>
On 2018-04-17 13:28, Sean Paul wrote:
> On Mon, Apr 16, 2018 at 05:40:13PM -0700, Chandan Uddaraju wrote:
>> For dual dsi mode, the horizontal timing needs
>> to be divided by half since both the dsi controllers
>> will be driving this panel. Adjust the pixel clock and
>> DSI timing accordingly.
>>
>> Changes in V2:
>> --Removed Change-Id from the commit text tags.
>
> You ignored my feedback on v1
>
Sorry Sean, I missed fixing your comment for this patch. I have uploaded
V3 patch series for review.
thanks
Chandan
>>
>> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
>> ---
>> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
>> drivers/gpu/drm/msm/dsi/dsi_host.c | 17 +++++++++++++++++
>> drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 +++++++++++++++
>> 3 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
>> b/drivers/gpu/drm/msm/dsi/dsi.h
>> index 70d9a9a..4131b47 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
>> @@ -161,6 +161,7 @@ void msm_dsi_host_cmd_xfer_commit(struct
>> mipi_dsi_host *host,
>> u32 dma_base, u32 len);
>> int msm_dsi_host_enable(struct mipi_dsi_host *host);
>> int msm_dsi_host_disable(struct mipi_dsi_host *host);
>> +void msm_dsi_host_adjust_timing_config(struct mipi_dsi_host *host);
>> int msm_dsi_host_power_on(struct mipi_dsi_host *host,
>> struct msm_dsi_phy_shared_timings *phy_shared_timings);
>> int msm_dsi_host_power_off(struct mipi_dsi_host *host);
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 7a03a94..66a21cb 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -2237,6 +2237,23 @@ static void msm_dsi_sfpb_config(struct
>> msm_dsi_host *msm_host, bool enable)
>> SFPB_GPREG_MASTER_PORT_EN(en));
>> }
>>
>> +void msm_dsi_host_adjust_timing_config(struct mipi_dsi_host *host)
>> +{
>> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>> + struct drm_display_mode *mode = NULL;
>> +
>> + mode = msm_host->mode;
>> +
>> + mutex_lock(&msm_host->dev_mutex);
>> + mode->htotal >>= 1;
>> + mode->hdisplay >>= 1;
>> + mode->hsync_start >>= 1;
>> + mode->hsync_end >>= 1;
>> +
>> + mode->clock >>= 1;
>> + mutex_unlock(&msm_host->dev_mutex);
>> +}
>> +
>> int msm_dsi_host_power_on(struct mipi_dsi_host *host,
>> struct msm_dsi_phy_shared_timings *phy_shared_timings)
>> {
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
>> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
>> index 4cb1cb6..8ef1c3d 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
>> @@ -627,6 +627,21 @@ static void dsi_mgr_bridge_mode_set(struct
>> drm_bridge *bridge,
>> msm_dsi_host_set_display_mode(host, adjusted_mode);
>> if (is_dual_dsi && other_dsi)
>> msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
>> +
>> + /*
>> + * For dual DSI mode, the current DRM mode has
>> + * the complete width of the panel. Since, the complete
>> + * panel is driven by two DSI controllers, the
>> + * horizontal timings and the pixel clock have to be
>> + * split between the two dsi controllers. Adjust the
>> + * DSI host timing structures accordingly.
>> + */
>> + if (is_dual_dsi) {
>> + msm_dsi_host_adjust_timing_config(host);
>> + if (other_dsi)
>> + msm_dsi_host_adjust_timing_config(other_dsi->host);
>> + }
>> +
>> }
>>
>> static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
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next prev parent reply other threads:[~2018-04-18 21:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-17 0:40 [DPU PATCH v2 0/2] Connector virtualization for Dual-DSI Chandan Uddaraju
2018-04-17 0:40 ` [DPU PATCH v2 1/2] drm/msm/dsi: adjust dsi timing for dual dsi mode Chandan Uddaraju
2018-04-17 20:28 ` Sean Paul
2018-04-18 21:51 ` chandanu-sgV2jX0FEOL9JmXXK+q4OQ [this message]
[not found] ` <1523925614-28337-1-git-send-email-chandanu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-04-17 0:40 ` [DPU PATCH v2 2/2] drm/msm/dsi: Use one connector for dual DSI mode Chandan Uddaraju
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