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Mon, 17 Nov 2025 05:53:09 -0800 (PST) Received: from [192.168.68.110] ([191.202.237.26]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c73a29d72csm5356110a34.14.2025.11.17.05.53.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 05:53:08 -0800 (PST) Message-ID: <90c8c636-44f2-42fa-804f-de00ac0c664e@ventanamicro.com> Date: Mon, 17 Nov 2025 10:53:04 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] target/riscv: Update MISA.C for Zc* extensions To: frank.chang@sifive.com, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" , Max Chou References: <20251114090134.1125646-1-frank.chang@sifive.com> <20251114090134.1125646-2-frank.chang@sifive.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20251114090134.1125646-2-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 11/14/25 6:01 AM, frank.chang@sifive.com wrote: > From: Frank Chang > > MISA.C is set if the following extensions are selected: > * Zca and not F. > * Zca, Zcf and F (but not D) is specified (RV32 only). > * Zca, Zcf and Zcd if D is specified (RV32 only). > * Zca, Zcd if D is specified (RV64 only). > > Therefore, we need to set MISA.C according to the rules for Zc* > extensions. > > Signed-off-by: Frank Chang > Reviewed-by: Max Chou > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 440626ddfad..da09a2417cc 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1150,6 +1150,36 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) > } > } > > +/* > + * MISA.C is set if the following extensions are selected: > + * - Zca and not F. > + * - Zca, Zcf and F (but not D) is specified on RV32. > + * - Zca, Zcf and Zcd if D is specified on RV32. > + * - Zca, Zcd if D is specified on RV64. > + */ > +static void riscv_cpu_update_misa_c(RISCVCPU *cpu) > +{ > + CPURISCVState *env = &cpu->env; > + > + if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) { > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); > + return; > + } > + > + if (riscv_cpu_mxl(env) == MXL_RV32 && > + cpu->cfg.ext_zca && cpu->cfg.ext_zcf && > + riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd : riscv_has_ext(env, RVF)) { > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); > + return; > + } > + > + if (riscv_cpu_mxl(env) == MXL_RV64 && > + cpu->cfg.ext_zca && cpu->cfg.ext_zcd) { > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); > + return; > + } > +} > + > void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > { > CPURISCVState *env = &cpu->env; > @@ -1157,6 +1187,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > riscv_cpu_init_implied_exts_rules(); > riscv_cpu_enable_implied_rules(cpu); > + riscv_cpu_update_misa_c(cpu); > > riscv_cpu_validate_misa_priv(env, &local_err); > if (local_err != NULL) {