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Tue, 10 Nov 2026 04:05:26 -0800 (PST) Received: from [10.127.122.226] ([5.195.0.150]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5c159702ae0sm240512e87.20.2026.11.10.04.05.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 04:05:25 -0800 (PST) Message-ID: <91a4fdf2-638c-442b-be29-59e05c8ba396@gmail.com> Date: Tue, 10 Nov 2026 16:05:22 +0400 X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] phy: exynos5-usbdrd: fix HS phy init count imbalance on Exynos2200 To: Soheyb , Vinod Koul , Krzysztof Kozlowski Cc: Neil Armstrong , Manivannan Sadhasivam , Peter Griffin , Alim Akhtar , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20261109221522.2796426-1-soheyb_boulaa@proton.me> Content-Language: en-US From: Ivaylo Ivanov In-Reply-To: <20261109221522.2796426-1-soheyb_boulaa@proton.me> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/10/26 02:15, Soheyb wrote: > exynos2200_usbdrd_utmi_init() calls phy_init() on the high-speed phy, > but exynos2200_usbdrd_phy_exit() never calls phy_exit() on it. The init > count of the high-speed phy therefore never drops back to zero: after > the first init, every later phy_init() of it returns early, and its > clocks and supplies stay enabled across an exit of the UTMI phy. > > When the high-speed phy loses power while the controller is suspended, > it is thus not set up again on resume, and the DWC3 core soft reset > times out: > > dwc3 11210000.usb: DWC3 controller soft reset failed > > Exit the high-speed phy when the UTMI phy exits, first, in the reverse > order of the init. > > Fixes: cc52a697f87e ("phy: exynos5-usbdrd: support Exynos USBDRD 3.2 4nm controller") > Cc: stable@vger.kernel.org > Signed-off-by: Soheyb > --- > Tested on a Google Pixel 9 (Tensor G4) with an out-of-tree port that > uses the Exynos2200 phy ops and powers the USB block off in system > sleep: without this change the soft reset failed on the first resume; > with it, USB came back after each of two system sleeps. Not tested on > Exynos2200 hardware. > > drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c > index 087d552..0bee928 100644 > --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c > +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c > @@ -1486,6 +1486,13 @@ static int exynos2200_usbdrd_phy_exit(struct phy *phy) > u32 reg; > int ret; > > + /* > + * The UTMI init initializes the high-speed phy; exit it in turn, so > + * that the next init sets it up again after it lost power. > + */ I think the function is pretty self-explanatory, so could drop the comment. Otherwise looks good to me, nice catch! Acked-by: Ivaylo Ivanov Best regards, Ivaylo > + if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) > + phy_exit(phy_drd->hs_phy); > + > ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); > if (ret) > return ret; From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC93F606A31C for ; Tue, 10 Nov 2026 12:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=kmLVVJp0; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20260707 header.b=KgWoyy9O DKIM-Signature: v=1; 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Tue, 10 Nov 2026 04:05:26 -0800 (PST) Received: from [10.127.122.226] ([5.195.0.150]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5c159702ae0sm240512e87.20.2026.11.10.04.05.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 04:05:25 -0800 (PST) Message-ID: <91a4fdf2-638c-442b-be29-59e05c8ba396@gmail.com> Date: Tue, 10 Nov 2026 16:05:22 +0400 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] phy: exynos5-usbdrd: fix HS phy init count imbalance on Exynos2200 To: Soheyb , Vinod Koul , Krzysztof Kozlowski Cc: Neil Armstrong , Manivannan Sadhasivam , Peter Griffin , Alim Akhtar , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20261109221522.2796426-1-soheyb_boulaa@proton.me> Content-Language: en-US From: Ivaylo Ivanov In-Reply-To: <20261109221522.2796426-1-soheyb_boulaa@proton.me> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_040529_153259_11CFA3AD X-CRM114-Status: GOOD ( 20.79 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 11/10/26 02:15, Soheyb wrote: > exynos2200_usbdrd_utmi_init() calls phy_init() on the high-speed phy, > but exynos2200_usbdrd_phy_exit() never calls phy_exit() on it. The init > count of the high-speed phy therefore never drops back to zero: after > the first init, every later phy_init() of it returns early, and its > clocks and supplies stay enabled across an exit of the UTMI phy. > > When the high-speed phy loses power while the controller is suspended, > it is thus not set up again on resume, and the DWC3 core soft reset > times out: > > dwc3 11210000.usb: DWC3 controller soft reset failed > > Exit the high-speed phy when the UTMI phy exits, first, in the reverse > order of the init. > > Fixes: cc52a697f87e ("phy: exynos5-usbdrd: support Exynos USBDRD 3.2 4nm controller") > Cc: stable@vger.kernel.org > Signed-off-by: Soheyb > --- > Tested on a Google Pixel 9 (Tensor G4) with an out-of-tree port that > uses the Exynos2200 phy ops and powers the USB block off in system > sleep: without this change the soft reset failed on the first resume; > with it, USB came back after each of two system sleeps. Not tested on > Exynos2200 hardware. > > drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c > index 087d552..0bee928 100644 > --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c > +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c > @@ -1486,6 +1486,13 @@ static int exynos2200_usbdrd_phy_exit(struct phy *phy) > u32 reg; > int ret; > > + /* > + * The UTMI init initializes the high-speed phy; exit it in turn, so > + * that the next init sets it up again after it lost power. > + */ I think the function is pretty self-explanatory, so could drop the comment. Otherwise looks good to me, nice catch! Acked-by: Ivaylo Ivanov Best regards, Ivaylo > + if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) > + phy_exit(phy_drd->hs_phy); > + > ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); > if (ret) > return ret; -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy