Re: [PATCH v2 2/2] ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

[Andrew Jeffery <andrew@codeconstruct.com.au>]

On Tue, 2026-11-03 at 20:47 +0900, Jacky Huang wrote:
> Add support for the NVIDIA MGX Vera C2 BMC based on the
> ASPEED AST2600 SoC.

Can you please expand the description of the platform? Why was it
designed and built? What's its purpose?

> 
> Signed-off-by: Jacky Huang <jackyhuang@nvidia.com>
> ---
> Changes in v2:
> - Specify the console and baud rate in stdout-path and drop bootargs.
> - Use generic GPIO expander, fan controller and regulator node names.
> - Fix gpio-line-names indentation and GPIO bank comment formatting.
> - Remove duplicate GPIO line names.
> 
>  arch/arm/boot/dts/aspeed/Makefile             |    1 +
>  .../aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts    | 1275 +++++++++++++++++
>  2 files changed, 1276 insertions(+)
>  create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts
> 
> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> index 6874b621d..e5c44d423 100644
> --- a/arch/arm/boot/dts/aspeed/Makefile
> +++ b/arch/arm/boot/dts/aspeed/Makefile
> @@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
>  	aspeed-bmc-microsoft-olympus.dtb \
>  	aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
>  	aspeed-bmc-nvidia-msx4-bmc.dtb \
> +	aspeed-bmc-nvidia-vr-c2-bmc.dtb \
>  	aspeed-bmc-opp-lanyang.dtb \
>  	aspeed-bmc-opp-mowgli.dtb \
>  	aspeed-bmc-opp-nicole.dtb \
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts
> new file mode 100644
> index 000000000..a044dfa00
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts
> @@ -0,0 +1,1275 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "aspeed-g6.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +#include <dt-bindings/i2c/i2c.h>
> +
> +/ {
> +	model = "AST2600 MGX Vera C2 BMC";
> +	compatible = "nvidia,vr-c2-bmc", "aspeed,ast2600";
> +
> +	aliases {
> +		i2c16 = &i2c_usbhub;
> +		i2c17 = &i2c_tpm;
> +		i2c18 = &i2c_dp;
> +		i2c19 = &i2c_rtc;
> +		i2c20 = &i2c_fan_ctrl0;
> +		i2c21 = &i2c_fan_ctrl1;
> +		i2c22 = &i2c_fan_iox;
> +		i2c23 = &i2c_fan_hsc;
> +		i2c30 = &i2c_mcio_c0c1_north0;
> +		i2c31 = &i2c_mcio_c0c1_north1;
> +		i2c32 = &i2c_mcio_c0c1_north2;
> +		i2c33 = &i2c_mcio_c0c1_north3;
> +		i2c34 = &i2c_mcio_c0c1_north4;
> +		i2c35 = &i2c_mcio_c0c1_north5;
> +		i2c36 = &i2c_mcio_c0c1_north6;
> +		i2c37 = &i2c_mcio_c0c1_north7;
> +		i2c40 = &i2c_mcio_c0_south0;
> +		i2c41 = &i2c_mcio_c0_south1;
> +		i2c42 = &i2c_mcio_c0_south2;
> +		i2c43 = &i2c_mcio_c0_south3;
> +		i2c44 = &i2c_mcio_c0_south4;
> +		i2c45 = &i2c_mcio_c0_south5;
> +		i2c46 = &i2c_mcio_c0_south6;
> +		i2c47 = &i2c_mcio_c0_south7;
> +		i2c50 = &i2c_mcio_c1_south0;
> +		i2c51 = &i2c_mcio_c1_south1;
> +		i2c52 = &i2c_mcio_c1_south2;
> +		i2c53 = &i2c_mcio_c1_south3;
> +		i2c54 = &i2c_mcio_c1_south4;
> +		i2c55 = &i2c_mcio_c1_south5;
> +		i2c56 = &i2c_mcio_c1_south6;
> +		i2c57 = &i2c_mcio_c1_south7;
> +		serial2 = &uart3;
> +		serial4 = &uart5;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial4:115200n8";
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		fault-led {
> +			gpios = <&exp7 12 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		power-led {
> +			gpios = <&exp7 8 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		uid-led {
> +			gpios = <&exp7 10 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x80000000>;
> +	};
> +
> +	standby_power_regulator: regulator-standby-power {
> +		compatible = "regulator-fixed";
> +		enable-active-high;
> +		gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>;
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-max-microvolt = <1800000>;
> +		regulator-min-microvolt = <1800000>;
> +		regulator-name = "standby_power";
> +	};
> +
> +	reserved-memory {
> +		ranges;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		framebuffer@9f000000 {
> +			reg = <0x9f000000 0x01000000>;
> +			no-map;
> +		};
> +
> +		ramoops@a0000000 {
> +			compatible = "ramoops";
> +			reg = <0xa0000000 0x100000>;
> +			max-reason = <2>;
> +			record-size = <0x10000>;
> +		};
> +
> +		framebuffer {
> +			compatible = "shared-dma-pool";
> +			alignment = <0x01000000>;
> +			reusable;
> +			size = <0x01000000>;
> +		};
> +
> +		video_engine_memory: jpegbuffer {
> +			compatible = "shared-dma-pool";
> +			alignment = <0x01000000>;
> +			reusable;
> +			size = <0x02000000>;
> +		};
> +	};
> +};
> +
> +/*
> + * NVIDIA multi-interface MCU enumerates as hid-generic by default
> + * and binds to hid-cp2112 at runtime
> + */
> +&ehci1 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	status = "okay";
> +
> +	hub@1 {
> +		compatible = "usb424,2514";
> +		reg = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		hub@2 {
> +			compatible = "usb424,2422";
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			hub@1 {
> +				compatible = "usb424,2514";
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				device@1 {
> +					compatible = "usb955,cf11";
> +					reg = <1>;
> +					#address-cells = <2>;
> +					#size-cells = <0>;
> +
> +					cp2112: interface@1 {
> +						compatible = "usbif955,cf11.config1.1";
> +						reg = <1 1>;
> +						#gpio-cells = <2>;
> +						gpio-controller;
> +						#interrupt-cells = <2>;
> +						interrupt-controller;
> +
> +						i2c {
> +							#address-cells = <1>;
> +							#size-cells = <0>;
> +
> +							/* CPU0 IROT/thermal/SOCAMM/JTAG */
> +							gpio@50 {
> +								compatible = "nxp,pca9555";
> +								reg = <0x50>;
> +								gpio-controller;
> +								#gpio-cells = <2>;
> +								interrupt-controller;
> +								#interrupt-cells = <2>;
> +								interrupt-parent = <&cp2112>;
> +								interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> +								gpio-line-names =
> +									"CPU0_IROT_RECOVERY_L_3V3-I",
> +									"CPU0_IROT_FATAL_ERR_L_3V3-I",
> +									"CPU0_OVERT_L-I",
> +									"C0_THERM_WARN_N-I",
> +									"C0_S0_THERM_OVERT_N-I",
> +									"CPU0_CHIPTHROT_L-I",
> +									"C0_SOCAMM_0_ID_PRSNT_N_1V8-I",
> +									"C0_SOCAMM_1_ID_PRSNT_N-I",
> +									"C0_SOCAMM_2_ID_PRSNT_N-I",
> +									"C0_SOCAMM_3_ID_PRSNT_N-I",
> +									"C0_SOCAMM_4_ID_PRSNT_N-I",
> +									"C0_SOCAMM_5_ID_PRSNT_N-I",
> +									"C0_SOCAMM_6_ID_PRSNT_N-I",
> +									"C0_SOCAMM_7_ID_PRSNT_N-I",
> +									"MCU_JTAG_BYPASS_CPU0_S-O",
> +									"MCU_JTAG_BYPASS_CPU0-O";

I assume the -{I,O} suffixes refer to input or output. Are they
necessary?

Andrew