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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from SA3PR11MB7554.namprd11.prod.outlook.com (2603:10b6:806:315::9) by BL4PR11MB8847.namprd11.prod.outlook.com (2603:10b6:208:5a7::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.15; Tue, 8 Sep 2026 06:14:45 +0000 Received: from SA3PR11MB7554.namprd11.prod.outlook.com ([fe80::3ec0:2280:db82:d67b]) by SA3PR11MB7554.namprd11.prod.outlook.com ([fe80::3ec0:2280:db82:d67b%5]) with mapi id 15.21.0382.014; Tue, 8 Sep 2026 06:14:45 +0000 Message-ID: <91fa997d-f197-42be-8fdf-9b5882554320@intel.com> Date: Tue, 8 Sep 2026 11:44:33 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/12] drm/i915/dip: Store and use AS SDP transmission line from crtc state To: "Kandpal, Suraj" , "intel-gfx@lists.freedesktop.org" , "intel-xe@lists.freedesktop.org" CC: "ville.syrjala@linux.intel.com" , "Murthy, Arun R" , "jani.nikula@linux.intel.com" References: <20260611073316.1439306-1-ankit.k.nautiyal@intel.com> <20260611073316.1439306-7-ankit.k.nautiyal@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: Content-Type: text/plain; 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Instead, compute and store the AS SDP transmission line >> in the crtc state and use it when programming the EMP_AS_SDP_TL register. >> >> We get the clear picture about the SDPs and guardband only in >> intel_dp_sdp_compute_config_late() therefore we must configure the AS SDP >> transmission line at this point when AS SDP is enabled in crtc_state. >> >> This prepares the ground for supporting programmable transmission lines for >> additional DP SDPs. >> >> Signed-off-by: Ankit Nautiyal >> --- >> drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ >> drivers/gpu/drm/i915/display/intel_dip.c | 20 +++++++++++--------- >> drivers/gpu/drm/i915/display/intel_dip.h | 3 +++ >> drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++++ >> 4 files changed, 27 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c >> b/drivers/gpu/drm/i915/display/intel_ddi.c >> index 6399b16405c8..d2edfad295d5 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> @@ -49,6 +49,7 @@ >> #include "intel_ddi.h" >> #include "intel_ddi_buf_trans.h" >> #include "intel_de.h" >> +#include "intel_dip.h" >> #include "intel_display_power.h" >> #include "intel_display_regs.h" >> #include "intel_display_types.h" >> @@ -4215,6 +4216,7 @@ static void intel_ddi_get_config(struct intel_encoder >> *encoder, >> intel_read_dp_sdp(encoder, pipe_config, >> HDMI_PACKET_TYPE_GAMUT_METADATA); >> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); >> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); >> + intel_dip_sdp_transmission_line_get_config(pipe_config); >> >> intel_audio_codec_get_config(encoder, pipe_config); } diff --git >> a/drivers/gpu/drm/i915/display/intel_dip.c >> b/drivers/gpu/drm/i915/display/intel_dip.c >> index 504a2edadd0e..333314637db5 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dip.c >> +++ b/drivers/gpu/drm/i915/display/intel_dip.c >> @@ -27,19 +27,21 @@ void intel_dip_write_emp_as_sdp_tl(const struct >> intel_crtc_state *crtc_state) { >> struct intel_display *display = to_intel_display(crtc_state); >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> - u32 transmission_line = 0; >> >> if (!HAS_EMP_AS_SDP_TL(display)) >> return; >> - /* >> - * Since currently we support VRR only for DP/eDP, program the register >> - * for Adaptive Sync SDP. For non-DP encoders, the register is reset >> - * to 0. >> - */ >> - if (intel_crtc_has_dp_encoder(crtc_state)) >> - transmission_line = >> intel_dp_get_as_sdp_transmission_line(crtc_state); >> >> intel_de_write(display, >> EMP_AS_SDP_TL(display, cpu_transcoder), >> - EMP_AS_SDP_DB_TL(transmission_line)); >> + EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl)); >> +} >> + >> +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state >> +*crtc_state) { >> + crtc_state->dip.emp_as_sdp_tl = >> +intel_dp_get_as_sdp_transmission_line(crtc_state); >> +} >> + >> +void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state >> +*crtc_state) { >> + crtc_state->dip.emp_as_sdp_tl = >> +intel_dip_read_emp_as_sdp_tl(crtc_state); >> } >> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h >> b/drivers/gpu/drm/i915/display/intel_dip.h >> index 37507ac3e645..600dabbf7372 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dip.h >> +++ b/drivers/gpu/drm/i915/display/intel_dip.h >> @@ -43,4 +43,7 @@ struct intel_dip { >> u16 emp_as_sdp_tl; >> }; >> >> +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state >> +*crtc_state); void intel_dip_sdp_transmission_line_get_config(struct >> +intel_crtc_state *crtc_state); >> + >> #endif /* __INTEL_DIP_H__ */ >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c >> b/drivers/gpu/drm/i915/display/intel_dp.c >> index f54f7faf878f..e143ec1b76d0 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -7356,6 +7356,8 @@ int intel_dp_sdp_compute_config_late(struct >> intel_crtc_state *crtc_state) >> return -EINVAL; >> } >> >> + intel_dip_sdp_tl_compute_config_late(crtc_state); >> + >> return 0; >> } >> >> @@ -7468,6 +7470,15 @@ void intel_dp_link_cleanup(struct intel_dp >> *intel_dp) >> >> int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state >> *crtc_state) { >> + struct intel_display *display = to_intel_display(crtc_state); >> + >> + if (!HAS_EMP_AS_SDP_TL(display)) >> + return 0; >> + >> + if (!(crtc_state->infoframes.enable & >> + intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))) >> + return 0; >> + > this part should not be a part of this maybe can be squashed with 4th patch where this function was introduced Agreed. Actually infoframe.enable check is not needed since we are computing the transmission line even if the packet is not sent. Since this is called only from DP/eDP compute config path now, for non-DP encoders it will not be set. I will remove the check and move the HAS_EMP_AS_SDP_TL() check in patch#4 where it belongs. Regards, Ankit > > Regards, > Suraj Kandpal > >> /* >> * EMP_AS_SDP_TL defines the T1 position as the default AS SDP >> * Transmission Line, which corresponds to the start of the >> -- >> 2.45.2