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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: "Sean Christopherson" <seanjc@google.com>,
	"Andrew Jones" <andrew.jones@linux.dev>,
	"Janosch Frank" <frankja@linux.ibm.com>,
	"Claudio Imbrenda" <imbrenda@linux.ibm.com>,
	"Nico Böhr" <nrb@linux.ibm.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>
Cc: kvm-riscv@lists.infradead.org, linux-s390@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH 06/16] x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES
Date: Tue, 10 Jun 2025 14:21:04 +0800	[thread overview]
Message-ID: <92b737d4-4584-4e8c-89dc-e2a5308449ec@linux.intel.com> (raw)
In-Reply-To: <20250529221929.3807680-7-seanjc@google.com>


On 5/30/2025 6:19 AM, Sean Christopherson wrote:
> Add a definition for X86_PROPERTY_INTEL_PT_NR_RANGES, and use it instead
> of open coding equivalent logic in the LA57 testcase that verifies the
> canonical address behavior of PT MSRs.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
>  lib/x86/processor.h | 3 +++
>  x86/la57.c          | 2 +-
>  2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/lib/x86/processor.h b/lib/x86/processor.h
> index cbfd2ee1..3b02a966 100644
> --- a/lib/x86/processor.h
> +++ b/lib/x86/processor.h
> @@ -370,6 +370,9 @@ struct x86_cpu_property {
>  
>  #define X86_PROPERTY_XSTATE_TILE_SIZE		X86_CPU_PROPERTY(0xd, 18, EAX,  0, 31)
>  #define X86_PROPERTY_XSTATE_TILE_OFFSET		X86_CPU_PROPERTY(0xd, 18, EBX,  0, 31)
> +
> +#define X86_PROPERTY_INTEL_PT_NR_RANGES		X86_CPU_PROPERTY(0x14, 1, EAX,  0, 2)
> +
>  #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES	X86_CPU_PROPERTY(0x1d, 0, EAX,  0, 31)
>  #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES	X86_CPU_PROPERTY(0x1d, 1, EAX,  0, 15)
>  #define X86_PROPERTY_AMX_BYTES_PER_TILE		X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
> diff --git a/x86/la57.c b/x86/la57.c
> index 41764110..1161a5bf 100644
> --- a/x86/la57.c
> +++ b/x86/la57.c
> @@ -288,7 +288,7 @@ static void __test_canonical_checks(bool force_emulation)
>  
>  	/* PT filter ranges */
>  	if (this_cpu_has(X86_FEATURE_INTEL_PT)) {
> -		int n_ranges = cpuid_indexed(0x14, 0x1).a & 0x7;
> +		int n_ranges = this_cpu_property(X86_PROPERTY_INTEL_PT_NR_RANGES);
>  		int i;
>  
>  		for (i = 0 ; i < n_ranges ; i++) {

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>



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WARNING: multiple messages have this Message-ID (diff)
From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: "Sean Christopherson" <seanjc@google.com>,
	"Andrew Jones" <andrew.jones@linux.dev>,
	"Janosch Frank" <frankja@linux.ibm.com>,
	"Claudio Imbrenda" <imbrenda@linux.ibm.com>,
	"Nico Böhr" <nrb@linux.ibm.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>
Cc: kvm-riscv@lists.infradead.org, linux-s390@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH 06/16] x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES
Date: Tue, 10 Jun 2025 14:21:04 +0800	[thread overview]
Message-ID: <92b737d4-4584-4e8c-89dc-e2a5308449ec@linux.intel.com> (raw)
In-Reply-To: <20250529221929.3807680-7-seanjc@google.com>


On 5/30/2025 6:19 AM, Sean Christopherson wrote:
> Add a definition for X86_PROPERTY_INTEL_PT_NR_RANGES, and use it instead
> of open coding equivalent logic in the LA57 testcase that verifies the
> canonical address behavior of PT MSRs.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
>  lib/x86/processor.h | 3 +++
>  x86/la57.c          | 2 +-
>  2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/lib/x86/processor.h b/lib/x86/processor.h
> index cbfd2ee1..3b02a966 100644
> --- a/lib/x86/processor.h
> +++ b/lib/x86/processor.h
> @@ -370,6 +370,9 @@ struct x86_cpu_property {
>  
>  #define X86_PROPERTY_XSTATE_TILE_SIZE		X86_CPU_PROPERTY(0xd, 18, EAX,  0, 31)
>  #define X86_PROPERTY_XSTATE_TILE_OFFSET		X86_CPU_PROPERTY(0xd, 18, EBX,  0, 31)
> +
> +#define X86_PROPERTY_INTEL_PT_NR_RANGES		X86_CPU_PROPERTY(0x14, 1, EAX,  0, 2)
> +
>  #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES	X86_CPU_PROPERTY(0x1d, 0, EAX,  0, 31)
>  #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES	X86_CPU_PROPERTY(0x1d, 1, EAX,  0, 15)
>  #define X86_PROPERTY_AMX_BYTES_PER_TILE		X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
> diff --git a/x86/la57.c b/x86/la57.c
> index 41764110..1161a5bf 100644
> --- a/x86/la57.c
> +++ b/x86/la57.c
> @@ -288,7 +288,7 @@ static void __test_canonical_checks(bool force_emulation)
>  
>  	/* PT filter ranges */
>  	if (this_cpu_has(X86_FEATURE_INTEL_PT)) {
> -		int n_ranges = cpuid_indexed(0x14, 0x1).a & 0x7;
> +		int n_ranges = this_cpu_property(X86_PROPERTY_INTEL_PT_NR_RANGES);
>  		int i;
>  
>  		for (i = 0 ; i < n_ranges ; i++) {

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>



  reply	other threads:[~2025-06-10  6:22 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-29 22:19 [kvm-unit-tests PATCH 00/16] x86: Add CPUID properties, clean up related code Sean Christopherson
2025-05-29 22:19 ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 01/16] lib: Add and use static_assert() convenience wrappers Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-30  6:03   ` Andrew Jones
2025-05-30  6:03     ` Andrew Jones
2025-05-30  9:01   ` Janosch Frank
2025-05-30  9:01     ` Janosch Frank
2025-06-10  6:04   ` Mi, Dapeng
2025-06-10  6:04     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 02/16] x86: Encode X86_FEATURE_* definitions using a structure Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:08   ` Mi, Dapeng
2025-06-10  6:08     ` Mi, Dapeng
2025-06-10 13:56     ` Sean Christopherson
2025-06-10 13:56       ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 03/16] x86: Add X86_PROPERTY_* framework to retrieve CPUID values Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:14   ` Mi, Dapeng
2025-06-10  6:14     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 04/16] x86: Use X86_PROPERTY_MAX_VIRT_ADDR in is_canonical() Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:16   ` Mi, Dapeng
2025-06-10  6:16     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 05/16] x86: Implement get_supported_xcr0() using X86_PROPERTY_SUPPORTED_XCR0_{LO,HI} Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:18   ` Mi, Dapeng
2025-06-10  6:18     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 06/16] x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:21   ` Mi, Dapeng [this message]
2025-06-10  6:21     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 07/16] x86/pmu: Rename pmu_gp_counter_is_available() to pmu_arch_event_is_available() Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:09   ` Mi, Dapeng
2025-06-10  7:09     ` Mi, Dapeng
2025-06-10 16:16     ` Sean Christopherson
2025-06-10 16:16       ` Sean Christopherson
2025-06-11  0:41       ` Mi, Dapeng
2025-06-11  0:41         ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 08/16] x86/pmu: Rename gp_counter_mask_length to arch_event_mask_length Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:22   ` Mi, Dapeng
2025-06-10  7:22     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 09/16] x86/pmu: Mark all arch events as available on AMD Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 10/16] x86/pmu: Use X86_PROPERTY_PMU_* macros to retrieve PMU information Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:29   ` Mi, Dapeng
2025-06-10  7:29     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 11/16] x86/sev: Use VC_VECTOR from processor.h Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:25   ` Mi, Dapeng
2025-06-10  7:25     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 12/16] x86/sev: Skip the AMD SEV test if SEV is unsupported/disabled Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 13/16] x86/sev: Define and use X86_FEATURE_* flags for CPUID 0x8000001F Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 14/16] x86/sev: Use X86_PROPERTY_SEV_C_BIT to get the AMD SEV C-bit location Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 15/16] x86/sev: Use amd_sev_es_enabled() to detect if SEV-ES is enabled Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-30 16:22   ` Liam Merwick
2025-05-30 16:22     ` Liam Merwick
2025-05-29 22:19 ` [kvm-unit-tests PATCH 16/16] x86: Move SEV MSR definitions to msr.h Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10 19:42 ` [kvm-unit-tests PATCH 00/16] x86: Add CPUID properties, clean up related code Sean Christopherson
2025-06-10 19:42   ` Sean Christopherson

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