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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd34f2af5sm7907937f8f.78.2025.02.10.11.42.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 11:42:30 -0800 (PST) Message-ID: <9455ed23-ddfb-436a-b1a9-cdd7d5c5dd0c@gmail.com> Date: Mon, 10 Feb 2025 20:42:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11 To: Alex Deucher , amd-gfx@lists.freedesktop.org Cc: Srinivasan Shanmugam , lin cao , Jingwen Chen , =?UTF-8?Q?Christian_K=C3=B6nig?= , Shaoyun Liu References: <20250210162755.2488728-1-alexander.deucher@amd.com> <20250210162755.2488728-2-alexander.deucher@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20250210162755.2488728-2-alexander.deucher@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 10.02.25 um 17:27 schrieb Alex Deucher: > From: Srinivasan Shanmugam > > This commit introduces enhancements to the handling of the cleaner > shader fence in the AMDGPU MES driver: > > - The MES (Microcode Execution Scheduler) now sends a PM4 packet to the > KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring > that requests are handled in a controlled manner and avoiding the > race conditions. > - The CP (Compute Processor) firmware has been updated to use a private > bus for accessing specific registers, avoiding unnecessary operations > that could lead to issues in VF (Virtual Function) mode. > - The cleaner shader fence memory address is now set correctly in the > `mes_set_hw_res_pkt` structure, allowing for proper synchronization of > the cleaner shader execution. This is done by calculating the address > using the write-back memory base address and the cleaner fence offset. > > Cc: lin cao > Cc: Jingwen Chen > Cc: Christian König > Cc: Alex Deucher > Suggested-by: Shaoyun Liu > Signed-off-by: Srinivasan Shanmugam > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 17 ++++++++++++----- > 1 file changed, 12 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > index e862a3febe2b2..661268172dcf6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > @@ -754,7 +754,7 @@ static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) > mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; > mes_set_hw_res_pkt.enable_mes_info_ctx = 1; > > - ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, > + ret = amdgpu_bo_create_kernel(adev, size + AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, You might want to adjust the size calculation earlier in the function instead of here. Christian. > AMDGPU_GEM_DOMAIN_VRAM, > &mes->resource_1, > &mes->resource_1_gpu_addr, > @@ -765,7 +765,10 @@ static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) > } > > mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; > - mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; > + mes_set_hw_res_pkt.mes_info_ctx_size = size; > + mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = > + mes->resource_1_gpu_addr + size; > + > return mes_v11_0_submit_pkt_and_poll_completion(mes, > &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), > offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); > @@ -1632,7 +1635,8 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) > if (r) > goto failure; > > - if (amdgpu_sriov_is_mes_info_enable(adev)) { > + if (amdgpu_sriov_is_mes_info_enable(adev) || > + adev->gfx.enable_cleaner_shader) { > r = mes_v11_0_set_hw_resources_1(&adev->mes); > if (r) { > DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); > @@ -1665,10 +1669,13 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) > static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) > { > struct amdgpu_device *adev = ip_block->adev; > - if (amdgpu_sriov_is_mes_info_enable(adev)) { > + > + if (amdgpu_sriov_is_mes_info_enable(adev) || > + adev->gfx.enable_cleaner_shader) { > amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, > - &adev->mes.resource_1_addr); > + &adev->mes.resource_1_addr); > } > + > return 0; > } >