From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1180DCCA468 for ; Tue, 30 Sep 2025 13:29:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80D3910E281; Tue, 30 Sep 2025 13:29:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="O9x7ZUq5"; dkim-atps=neutral Received: from sea.source.kernel.org (sea.source.kernel.org [172.234.252.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D64810E281; Tue, 30 Sep 2025 13:29:48 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id EDE3640224; Tue, 30 Sep 2025 13:29:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 855C9C4CEF0; Tue, 30 Sep 2025 13:29:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759238987; bh=2mNRkO9895KuplaO7v8bPeKZOuVQGEIkzl/k8sMNe6s=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=O9x7ZUq5o9iok8ZSoYSD3MeFOL8wFGM/+3o8IGsH8vIbhMoKyXUbAvCkPohxzsPMe NAX9a/Ri6mfQYXWz3e7T3qAWjKWvNlTE/f+zRWgIT1arWSYmBSP7n0lryE9UskNAhy lUyj0VM5/dnhReNfmz2Hj4nGA+5bNExU6rOTeL4Mw0cuUuD7HpAacW0BV3kDV+LSQG JyZIjIacD6YZ+JfRw03VvUdjrnEaZU3IWXvOAHMIwBrldSUQvTXJmsXL2McDqb7O9N dVoFCukBipxWDvYRSNP6Rx2+KXVqUVrKwYqF789RAbds5fifyRyhfXi2yZhtXnTcPl jGGvxvHqPjvsQ== Message-ID: <94bbd268-efbe-4ff6-ba09-e6254709d981@kernel.org> Date: Tue, 30 Sep 2025 15:29:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/13] gpu: nova-core: Set correct DMA mask To: Alistair Popple Cc: rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, acourbot@nvidia.com, Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?Q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , John Hubbard , Joel Fernandes , Timur Tabi , linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org References: <20250930131648.411720-1-apopple@nvidia.com> <20250930131648.411720-2-apopple@nvidia.com> From: Danilo Krummrich Content-Language: en-US In-Reply-To: <20250930131648.411720-2-apopple@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" On 9/30/25 3:16 PM, Alistair Popple wrote: > + // SAFETY: No DMA allocations have been made yet > + unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<47>())? }; I think you forgot to derive the value from the relevant sources, i.e. physical bus, DMA controller and MMU capabilities. I assume not all GPU architectures / generations have the exact same capabilities?