From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout08.his.huawei.com (canpmsgout08.his.huawei.com [113.46.200.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64724385D73 for ; Wed, 24 Jun 2026 08:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.223 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782290650; cv=none; b=IR/OsnzbzibEO638up8Q2CsKt/OMBmYKYr41i39wPD4unAsC5NcJOyEWYQXjwAA5r9CzMGDHekn+FjdqkvAuMpVvDuPWAcRpSmnWHke+dQ6/M54Vi99L1WS7oJUs8LQ2GRcR62+l3Ag4CAASI6WXrV3+Uc9/EY7IqyxhBSQiIf4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782290650; c=relaxed/simple; bh=pGA8jQpe5qpIW/z89pLHgBQK8B6wmXQkvKABO9HzjtA=; h=From:To:CC:Subject:Date:Message-ID:References:Content-Type: MIME-Version; b=PpfJqdPXiCYwRtzLpTvyeNFqD5RrrZzbj0ZDrL2NwJF1GUIj/A9R+pr4fKMAin9TX86T+AnRSemlloRt5Kl1Zww1tKxATUGoieMpayIMtKkr2vDsLt1zbYXmd3dXFZzGXuGO4ILoEqg4EpINVTDMw/psKroaJNR1YLlv/dsYhzk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=u0sf6IG5; arc=none smtp.client-ip=113.46.200.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="u0sf6IG5" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=gD81xbw18Sh9jn/7ZkMEu1F+TbHXFsYKEWWUgrlI2Xc=; b=u0sf6IG5D/RnwvoqPmgUG3+lv0KH4okdvJJ2aeX9mzlU8TZJwoM6fvjtlygYu25FLNWn0/7zH aoA01BqOs7GoNA5SW/4ya5aiNGkkHLuRnAE6RWFyZsYbY6YK4pRUBTvIBrQHrHx8XyEykfMc3lJ z21dNanHQ5Ah4mHYehD+UCU= Received: from mail.maildlp.com (unknown [172.19.163.15]) by canpmsgout08.his.huawei.com (SkyGuard) with ESMTPS id 4glZxS5SG1zmV7b; Wed, 24 Jun 2026 16:34:52 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id 4480D40571; Wed, 24 Jun 2026 16:43:58 +0800 (CST) Received: from kwepemq200014.china.huawei.com (7.202.195.213) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 24 Jun 2026 16:43:58 +0800 Received: from dggpemf100008.china.huawei.com (7.185.36.138) by kwepemq200014.china.huawei.com (7.202.195.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 24 Jun 2026 16:43:57 +0800 Received: from dggpemf100008.china.huawei.com ([7.185.36.138]) by dggpemf100008.china.huawei.com ([7.185.36.138]) with mapi id 15.02.1544.011; Wed, 24 Jun 2026 16:43:57 +0800 From: "chenjun (AM)" To: Robin Murphy , "will@kernel.org" , "joro@8bytes.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" CC: "zhangyuwei (G)" Subject: Re: [PATCH] iommu/arm-smmu-v3: Add tracepoint for EVTQ events Thread-Topic: [PATCH] iommu/arm-smmu-v3: Add tracepoint for EVTQ events Thread-Index: AQHc+zWJu1K6BmDmK0WFfh1OITwYNg== Date: Wed, 24 Jun 2026 08:43:57 +0000 Message-ID: <94eee9fa08a8461893b4e076919e9e55@huawei.com> References: <20260613130007.18563-1-chenjun102@huawei.com> <59c283b1-0436-4ea1-8feb-996dba617b6d@arm.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 =1B$B:_=1B(B 2026/6/23 23:31, Robin Murphy =1B$B On 13/06/2026 2:00 pm, Chen Jun wrote:=0A= >> Events reported by the SMMU can severely impact accelerator=0A= >> performance. Currently, only events that the SMMU fails to handle are=0A= >> printed to the kernel log, leaving most events invisible to users.=0A= >> To analyze and optimize accelerator performance, complete visibility=0A= >> into all SMMU-reported events is required.=0A= > =0A= > What events, exactly? AFAICS the only events we should expect to handle= =0A= > "invisibly", without being some unexpected error condition worth=0A= > screaming about, would be stalls for SVA page faults, and if SVA isn't=0A= > generically accounting page faults itself then I would imagine it=0A= > probably should.=0A= > =0A= > Thanks,=0A= > Robin.=0A= > =0A= =0A= AF and WP faults are common occurrences. and they can significantly =0A= impact SMMU performance. If we can determine exactly at which address =0A= and what type of page fault occurred, it would help us avoid SVA page =0A= fault events through other means. Also, I don't see any separate =0A= accounting for page fault events in the SVA flow.=0A= =0A= Thanks=0A= Chen Jun=0A= =0A= >> Add a tracepoint in the EVTQ interrupt handler to capture every=0A= >> event record reported by the SMMU. This allows users to collect all=0A= >> event information via ftrace/perf for further analysis, complementing=0A= >> the existing event decoder and error dump which only cover a subset=0A= >> of events.=0A= >>=0A= >> Signed-off-by: Chen Jun =0A= >> ---=0A= >> drivers/iommu/arm/arm-smmu-v3/Makefile | 2 +-=0A= >> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 ++=0A= >> drivers/iommu/arm/arm-smmu-v3/trace.c | 9 ++++=0A= >> drivers/iommu/arm/arm-smmu-v3/trace.h | 53 ++++++++++++++++++++= +=0A= >> 4 files changed, 66 insertions(+), 1 deletion(-)=0A= >> create mode 100644 drivers/iommu/arm/arm-smmu-v3/trace.c=0A= >> create mode 100644 drivers/iommu/arm/arm-smmu-v3/trace.h=0A= >>=0A= >> diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/= arm-smmu-v3/Makefile=0A= >> index 493a659cc66b..63a8d71bfc93 100644=0A= >> --- a/drivers/iommu/arm/arm-smmu-v3/Makefile=0A= >> +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile=0A= >> @@ -1,6 +1,6 @@=0A= >> # SPDX-License-Identifier: GPL-2.0=0A= >> obj-$(CONFIG_ARM_SMMU_V3) +=3D arm_smmu_v3.o=0A= >> -arm_smmu_v3-y :=3D arm-smmu-v3.o=0A= >> +arm_smmu_v3-y :=3D arm-smmu-v3.o trace.o=0A= >> arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) +=3D arm-smmu-v3-iommufd.o= =0A= >> arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) +=3D arm-smmu-v3-sva.o=0A= >> arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) +=3D tegra241-cmdqv.o=0A= >> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu= /arm/arm-smmu-v3/arm-smmu-v3.c=0A= >> index e8d7dbe495f0..85e6c25b73ed 100644=0A= >> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c=0A= >> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c=0A= >> @@ -34,6 +34,8 @@=0A= >> #include "arm-smmu-v3.h"=0A= >> #include "../../dma-iommu.h"=0A= >> =0A= >> +#include "trace.h"=0A= >> +=0A= >> static bool disable_msipolling;=0A= >> module_param(disable_msipolling, bool, 0444);=0A= >> MODULE_PARM_DESC(disable_msipolling,=0A= >> @@ -2271,6 +2273,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, v= oid *dev)=0A= >> =0A= >> do {=0A= >> while (!queue_remove_raw(q, evt)) {=0A= >> + trace_smmu_evtq_event(smmu, evt);=0A= >> arm_smmu_decode_event(smmu, evt, &event);=0A= >> if (arm_smmu_handle_event(smmu, evt, &event))=0A= >> arm_smmu_dump_event(smmu, evt, &event, &rs);=0A= >> diff --git a/drivers/iommu/arm/arm-smmu-v3/trace.c b/drivers/iommu/arm/a= rm-smmu-v3/trace.c=0A= >> new file mode 100644=0A= >> index 000000000000..77378698b1a3=0A= >> --- /dev/null=0A= >> +++ b/drivers/iommu/arm/arm-smmu-v3/trace.c=0A= >> @@ -0,0 +1,9 @@=0A= >> +// SPDX-License-Identifier: GPL-2.0=0A= >> +/*=0A= >> + * ARM SMMUv3 trace support=0A= >> + *=0A= >> + * Copyright (c) 2026 OpenCloudOS / openEuler=0A= >> + */=0A= >> +=0A= >> +#define CREATE_TRACE_POINTS=0A= >> +#include "trace.h"=0A= >> diff --git a/drivers/iommu/arm/arm-smmu-v3/trace.h b/drivers/iommu/arm/a= rm-smmu-v3/trace.h=0A= >> new file mode 100644=0A= >> index 000000000000..7cec8d41745e=0A= >> --- /dev/null=0A= >> +++ b/drivers/iommu/arm/arm-smmu-v3/trace.h=0A= >> @@ -0,0 +1,53 @@=0A= >> +/* SPDX-License-Identifier: GPL-2.0 */=0A= >> +/*=0A= >> + * ARM SMMUv3 trace support=0A= >> + *=0A= >> + * Copyright (c) 2026 OpenCloudOS / openEuler=0A= >> + */=0A= >> +=0A= >> +#undef TRACE_SYSTEM=0A= >> +#define TRACE_SYSTEM arm_smmu_v3=0A= >> +=0A= >> +#if !defined(_TRACE_ARM_SMMU_V3_H) || defined(TRACE_HEADER_MULTI_READ)= =0A= >> +#define _TRACE_ARM_SMMU_V3_H=0A= >> +=0A= >> +#include =0A= >> +=0A= >> +#include "arm-smmu-v3.h"=0A= >> +=0A= >> +TRACE_EVENT(smmu_evtq_event,=0A= >> +=0A= >> + TP_PROTO(struct arm_smmu_device *smmu, u64 *evt),=0A= >> +=0A= >> + TP_ARGS(smmu, evt),=0A= >> +=0A= >> + TP_STRUCT__entry(=0A= >> + __string(iommu, dev_name(smmu->dev))=0A= >> + __field(u64, evt0)=0A= >> + __field(u64, evt1)=0A= >> + __field(u64, evt2)=0A= >> + __field(u64, evt3)=0A= >> + ),=0A= >> +=0A= >> + TP_fast_assign(=0A= >> + __assign_str(iommu);=0A= >> + __entry->evt0 =3D evt[0];=0A= >> + __entry->evt1 =3D evt[1];=0A= >> + __entry->evt2 =3D evt[2];=0A= >> + __entry->evt3 =3D evt[3];=0A= >> + ),=0A= >> +=0A= >> + TP_printk("%s evt: 0x%016llx 0x%016llx 0x%016llx 0x%016llx",=0A= >> + __get_str(iommu),=0A= >> + __entry->evt0, __entry->evt1,=0A= >> + __entry->evt2, __entry->evt3)=0A= >> +);=0A= >> +=0A= >> +#endif /* _TRACE_ARM_SMMU_V3_H */=0A= >> +=0A= >> +/* This part must be outside protection */=0A= >> +#undef TRACE_INCLUDE_PATH=0A= >> +#undef TRACE_INCLUDE_FILE=0A= >> +#define TRACE_INCLUDE_PATH ../../drivers/iommu/arm/arm-smmu-v3/=0A= >> +#define TRACE_INCLUDE_FILE trace=0A= >> +#include =0A= > =0A= > =0A= > =0A= =0A=