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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4399bea8577sm62359265e9.0.2025.02.21.02.11.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Feb 2025 02:11:59 -0800 (PST) Message-ID: <950f4531-7614-4327-856f-45a2a2f9cd21@redhat.com> Date: Fri, 21 Feb 2025 11:11:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH rfcv2 09/20] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Content-Language: en-US To: Zhenzhong Duan , qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost References: <20250219082228.3303163-1-zhenzhong.duan@intel.com> <20250219082228.3303163-10-zhenzhong.duan@intel.com> From: Eric Auger In-Reply-To: <20250219082228.3303163-10-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.457, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Zhenzhong, On 2/19/25 9:22 AM, Zhenzhong Duan wrote: > In early days vtd_ce_get_rid2pasid_entry() is used to get pasid entry of is/was > rid2pasid, then extend to any pasid. So a new name vtd_ce_get_pasid_entry then it was extended to get any pasid entry? > is better to match its functions. to match what it actually does? I do not know the vtd spec very well so I searched for rid2pasid and I did not find any reference. I think I understand what is the pasid entry from the pasid table though so the renaming does make sense to me. Eric > > No functional change intended. > > Signed-off-by: Zhenzhong Duan > --- > hw/i386/intel_iommu.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 7fde0603bf..df5fb30bc8 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -944,7 +944,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s, > return 0; > } > > -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, > +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, > VTDContextEntry *ce, > VTDPASIDEntry *pe, > uint32_t pasid) > @@ -1025,7 +1025,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, > VTDPASIDEntry pe; > > if (s->root_scalable) { > - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); > + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); > if (s->flts) { > return VTD_PE_GET_FL_LEVEL(&pe); > } else { > @@ -1048,7 +1048,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, > VTDPASIDEntry pe; > > if (s->root_scalable) { > - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); > + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); > return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; > } > > @@ -1116,7 +1116,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, > VTDPASIDEntry pe; > > if (s->root_scalable) { > - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); > + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); > if (s->flts) { > return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; > } else { > @@ -1522,7 +1522,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, > * has valid rid2pasid setting, which includes valid > * rid2pasid field and corresponding pasid entry setting > */ > - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); > + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); > } > > /* Map a device to its corresponding domain (context-entry) */ > @@ -1611,7 +1611,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, > VTDPASIDEntry pe; > > if (s->root_scalable) { > - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); > + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); > return VTD_SM_PASID_ENTRY_DID(pe.val[1]); > } > > @@ -1687,7 +1687,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VTDContextEntry *ce, > int ret; > > if (s->root_scalable) { > - ret = vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); > + ret = vtd_ce_get_pasid_entry(s, ce, &pe, pasid); > if (ret) { > /* > * This error is guest triggerable. We should assumt PT