From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "robh@kernel.org" <robh@kernel.org>,
"mchehab@kernel.org" <mchehab@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"Bo Kong (孔波)" <Bo.Kong@mediatek.com>
Cc: "linux-media@vger.kernel.org" <linux-media@vger.kernel.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Subject: Re: [PATCH v3 3/4] media: mediatek: add MT8188 AIE driver
Date: Thu, 26 Dec 2024 03:53:57 +0000 [thread overview]
Message-ID: <95345df12095e976fedfcfcc6aac77f5d6a2d2b8.camel@mediatek.com> (raw)
In-Reply-To: <20241225090113.17027-4-bo.kong@mediatek.com>
On Wed, 2024-12-25 at 17:00 +0800, bo.kong wrote:
> From: Bo Kong <Bo.Kong@mediatek.com>
>
> Add a V4L2 sub-device driver for MT8188 AIE.
>
> Signed-off-by: Bo Kong <Bo.Kong@mediatek.com>
> ---
[snip]
> +#define FLD_PL_IN_BASE_ADDR_0_0 0x550
> +#define FLD_PL_IN_BASE_ADDR_0_1 0x554
> +#define FLD_PL_IN_BASE_ADDR_0_2 0x558
> +#define FLD_PL_IN_BASE_ADDR_0_3 0x55C
> +#define FLD_PL_IN_BASE_ADDR_0_4 0x560
> +#define FLD_PL_IN_BASE_ADDR_0_5 0x564
> +#define FLD_PL_IN_BASE_ADDR_0_6 0x568
> +#define FLD_PL_IN_BASE_ADDR_0_7 0x56C
> +#define FLD_PL_IN_BASE_ADDR_0_8 0x570
> +#define FLD_PL_IN_BASE_ADDR_0_9 0x574
> +#define FLD_PL_IN_BASE_ADDR_0_10 0x578
> +#define FLD_PL_IN_BASE_ADDR_0_11 0x57C
> +#define FLD_PL_IN_BASE_ADDR_0_12 0x580
> +#define FLD_PL_IN_BASE_ADDR_0_13 0x584
> +#define FLD_PL_IN_BASE_ADDR_0_14 0x588
> +#define FLD_PL_IN_BASE_ADDR_0_15 0x58C
> +#define FLD_PL_IN_BASE_ADDR_0_16 0x590
> +#define FLD_PL_IN_BASE_ADDR_0_17 0x594
> +#define FLD_PL_IN_BASE_ADDR_0_18 0x598
> +#define FLD_PL_IN_BASE_ADDR_0_19 0x59C
> +#define FLD_PL_IN_BASE_ADDR_0_20 0x5A0
> +#define FLD_PL_IN_BASE_ADDR_0_21 0x5A4
> +#define FLD_PL_IN_BASE_ADDR_0_22 0x5A8
> +#define FLD_PL_IN_BASE_ADDR_0_23 0x5AC
> +#define FLD_PL_IN_BASE_ADDR_0_24 0x5B0
> +#define FLD_PL_IN_BASE_ADDR_0_25 0x5B4
> +#define FLD_PL_IN_BASE_ADDR_0_26 0x5B8
> +#define FLD_PL_IN_BASE_ADDR_0_27 0x5BC
> +#define FLD_PL_IN_BASE_ADDR_0_28 0x5C0
> +#define FLD_PL_IN_BASE_ADDR_0_29 0x5C4
> +
[snip]
> +void aie_execute(struct mtk_aie_dev *fd, struct aie_enq_info *aie_cfg)
> +{
> + unsigned int loop_num = 0;
> + unsigned int loop_reg_val = 0;
> + unsigned int i = 0;
> +
> + if (aie_cfg->sel_mode == FDMODE) {
> + writel(0x0, fd->fd_base + AIE_START_REG);
> + writel(0x00000111, fd->fd_base + AIE_ENABLE_REG);
> + loop_num = FD_LOOP_NUM / 3 * (aie_cfg->number_of_pyramid);
> + loop_reg_val = (loop_num << 8) |
> + (aie_cfg->number_of_pyramid - 1);
> + writel(loop_reg_val, fd->fd_base + AIE_LOOP_REG);
> + writel(0x1, fd->fd_base + AIE_INT_EN_REG);
> + writel(fd->reg_cfg.rs_adr,
> + fd->fd_base + AIE_RS_CON_BASE_ADR_REG);
> + writel(fd->reg_cfg.fd_adr,
> + fd->fd_base + AIE_FD_CON_BASE_ADR_REG);
> + writel(fd->reg_cfg.yuv2rgb_adr,
> + fd->fd_base + AIE_YUV2RGB_CON_BASE_ADR_REG);
> +
> + if (fd->variant->hw_version == 31) {
> + writel(0x00000002,
> + fd->fd_base + AIE_YUV2RGB_CON_BASE_ADR_MSB);
> + writel(0x00000002,
> + fd->fd_base + AIE_RS_CON_BASE_ADR_MSB);
> + writel(0x00000002,
> + fd->fd_base + AIE_FD_CON_BASE_ADR_MSB);
> + }
> +
> + writel(0x1, fd->fd_base + AIE_START_REG);
> + } else if (aie_cfg->sel_mode == ATTRIBUTEMODE) {
> + writel(0x0, fd->fd_base + AIE_START_REG);
> + writel(0x00000101, fd->fd_base + AIE_ENABLE_REG);
> + writel(0x00001A00, fd->fd_base + AIE_LOOP_REG);
> + writel(0x1, fd->fd_base + AIE_INT_EN_REG);
> + writel(fd->reg_cfg.rs_adr,
> + fd->fd_base + AIE_RS_CON_BASE_ADR_REG);
> + writel(fd->reg_cfg.fd_adr,
> + fd->fd_base + AIE_FD_CON_BASE_ADR_REG);
> + writel(fd->reg_cfg.yuv2rgb_adr,
> + fd->fd_base + AIE_YUV2RGB_CON_BASE_ADR_REG);
> +
> + if (fd->variant->hw_version == 31) {
> + writel(0x00000002,
> + fd->fd_base + AIE_YUV2RGB_CON_BASE_ADR_MSB);
> + writel(0x00000002,
> + fd->fd_base + AIE_RS_CON_BASE_ADR_MSB);
> + writel(0x00000002,
> + fd->fd_base + AIE_FD_CON_BASE_ADR_MSB);
> + }
> +
> + writel(0x1, fd->fd_base + AIE_START_REG);
> + } else if (aie_cfg->sel_mode == FLDMODE) {
> + if (fd->variant->fld_enable) {
> + writel(0x10, fd->fd_base + AIE_START_REG);
> + writel(0x00011111, fd->fd_base + AIE_DMA_CTL_REG);
> + writel(0x01111111, fd->fd_base + FLD_EN);
> + writel(0x1, fd->fd_base + AIE_INT_EN_REG);
> + for (i = 0; i < aie_cfg->fld_face_num; i++) {
> + writel(aie_cfg->src_img_addr,
> + fd->fd_base + FLD_BASE_ADDR_FACE_0 +
> + i * 0x4);
> + writel(aie_cfg->fld_input[i].fld_in_crop_x1
> + << 16 |
> + aie_cfg->fld_input[i]
> + .fld_in_crop_y1,
> + fd->fd_base + fld_face_info_0[i]);
> + writel(aie_cfg->fld_input[i].fld_in_crop_x2
> + << 16 |
> + aie_cfg->fld_input[i]
> + .fld_in_crop_y2,
> + fd->fd_base + fld_face_info_1[i]);
> + writel(aie_cfg->fld_input[i].fld_in_rip << 4 |
> + aie_cfg->fld_input[i].fld_in_rop,
> + fd->fd_base + fld_face_info_2[i]);
> + }
> +
> + writel(aie_cfg->fld_face_num << 28 | FLD_FOREST << 16 |
> + FLD_POINT,
> + fd->fd_base + FLD_MODEL_PARA1);
> + writel(13 << 16 | 0xfe9,
> + fd->fd_base + FLD_MODEL_PARA14);
> +
> + writel(aie_cfg->src_img_width << 16 |
> + aie_cfg->src_img_height,
> + fd->fd_base + FLD_SRC_WD_HT);
> +
> + /*input settings*/
> + writel(0x007c003f, fd->fd_base + FLD_PL_IN_SIZE_0);
> + writel(0x0040000f, fd->fd_base + FLD_PL_IN_STRIDE_0);
> + writel(0x007c003f, fd->fd_base + FLD_PL_IN_SIZE_1);
> + writel(0x0040000f, fd->fd_base + FLD_PL_IN_STRIDE_1);
> + writel(0x0016003f, fd->fd_base + FLD_PL_IN_SIZE_2_0);
> + writel(0x0040000f, fd->fd_base + FLD_PL_IN_STRIDE_2_0);
> + writel(0x0013003f, fd->fd_base + FLD_PL_IN_SIZE_2_1);
> + writel(0x0040000f, fd->fd_base + FLD_PL_IN_STRIDE_2_1);
> + writel(0x0013003f, fd->fd_base + FLD_PL_IN_SIZE_2_2);
> + writel(0x0040000f, fd->fd_base + FLD_PL_IN_STRIDE_2_2);
> + writel(0x00a6001f, fd->fd_base + FLD_PL_IN_SIZE_3);
> + writel(0x0020000f, fd->fd_base + FLD_PL_IN_STRIDE_3);
> +
> + /*output setting*/
> + writel((2400 * aie_cfg->fld_face_num - 1) << 16 | 127,
> + fd->fd_base + FLD_SH_IN_SIZE_0);
> + writel(0x0010000f, fd->fd_base + FLD_SH_IN_STRIDE_0);
> + writel(fd->fld_para->fld_output_pa[0],
> + fd->fd_base + FLD_TR_OUT_BASE_ADDR_0);
> + writel((aie_cfg->fld_face_num - 1) << 16 | 0x6f,
> + fd->fd_base + FLD_TR_OUT_SIZE_0);
> + writel(0x0070000f, fd->fd_base + FLD_TR_OUT_STRIDE_0);
> + writel(fd->fld_para->fld_output_pa[0],
> + fd->fd_base + FLD_PP_OUT_BASE_ADDR_0);
> + writel((aie_cfg->fld_face_num - 1) << 16 | 0x6f,
> + fd->fd_base + FLD_PP_OUT_SIZE_0);
> + writel(0x0070000f, fd->fd_base + FLD_PP_OUT_STRIDE_0);
> +
> + /*cv score*/
> + writel(0x00000001, fd->fd_base + FLD_BS_BIAS);
> + writel(0x0000b835,
> + fd->fd_base + FLD_CV_FM_RANGE_0); // 8E8
> + writel(0xffff5cba,
> + fd->fd_base + FLD_CV_FM_RANGE_1); // 8EC
> + writel(0x00005ed5,
> + fd->fd_base + FLD_CV_PM_RANGE_0); // 8F0
> + writel(0xffff910d,
> + fd->fd_base + FLD_CV_PM_RANGE_1); // 8F4
> + writel(0x0000031e, fd->fd_base + FLD_BS_RANGE_0); // 8F8
> + writel(0xfffffcae, fd->fd_base + FLD_BS_RANGE_1); // 8FC
> +
> + /* 6 steps */
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_BLINK][14],
> + fd->fd_base + FLD_BS_IN_BASE_ADDR_14);
> +
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][0],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_0);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][1],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_1);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][2],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_2);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][3],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_3);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][4],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_4);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][5],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_5);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][6],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_6);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][7],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_7);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][8],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_8);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][9],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_9);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][10],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_10);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][11],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_11);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][12],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_12);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][13],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_13);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_CV][14],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_14);
> +
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][0],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_0);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][1],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_1);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][2],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_2);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][3],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_3);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][4],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_4);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][5],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_5);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][6],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_6);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][7],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_7);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][8],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_8);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][9],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_9);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][10],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_10);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][11],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_11);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][12],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_12);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][13],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_13);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_FP][14],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_14);
> +
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][0],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_0);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][1],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_1);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][2],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_2);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][3],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_3);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][4],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_4);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][5],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_5);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][6],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_6);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][7],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_7);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][8],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_8);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][9],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_9);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][10],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_10);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][11],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_11);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][12],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_12);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][13],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_13);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_LEAF][14],
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_14);
> +
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][0],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_0);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][1],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_1);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][2],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_2);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][3],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_3);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][4],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_4);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][5],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_5);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][6],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_6);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][7],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_7);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][8],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_8);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][9],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_9);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][10],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_10);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][11],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_11);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][12],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_12);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][13],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_13);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][14],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_14);
Use a for-loop to simplify these code:
#define FLD_PL_IN_BASE_ADDR_0_(n) (0x550 + 4 * n)
for (i = 0; i < 15; i++)
writel(fd->fld_para->fld_step_pa[FLD_STEP_KM02][i],
fd->fd_base + FLD_PL_IN_BASE_ADDR_0_(i));
Regards,
CK
> +
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][0],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_0);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][1],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_1);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][2],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_2);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][3],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_3);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][4],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_4);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][5],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_5);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][6],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_6);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][7],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_7);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][8],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_8);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][9],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_9);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][10],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_10);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][11],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_11);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][12],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_12);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][13],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_13);
> + writel(fd->fld_para->fld_step_pa[FLD_STEP_KM13][14],
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_14);
> +
> + /* */
> + writel(0x22222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_0_7_MSB);
> + writel(0x02222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_0_8_15_MSB);
> +
> + writel(0x22222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_0_7_MSB);
> + writel(0x02222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_1_8_15_MSB);
> +
> + writel(0x22222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_0_7_MSB);
> + writel(0x02222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_2_8_15_MSB);
> +
> + writel(0x22222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_0_7_MSB);
> + writel(0x02222222,
> + fd->fd_base + FLD_PL_IN_BASE_ADDR_3_8_15_MSB);
> +
> + writel(0x22222222,
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_0_7_MSB);
> + writel(0x02222222,
> + fd->fd_base + FLD_SH_IN_BASE_ADDR_8_15_MSB);
> +
> + writel(0x02000000,
> + fd->fd_base + FLD_BS_IN_BASE_ADDR_8_15_MSB);
> +
> + writel(0x22222222,
> + fd->fd_base + FLD_BASE_ADDR_FACE_0_7_MSB);
> + writel(0x02222222,
> + fd->fd_base + FLD_BASE_ADDR_FACE_8_14_MSB);
> + writel(0x00000002,
> + fd->fd_base + FLD_TR_OUT_BASE_ADDR_0_MSB);
> + writel(0x00000002,
> + fd->fd_base + FLD_PP_OUT_BASE_ADDR_0_MSB);
> +
> + /*fld mode + trigger start*/
> + writel(0x11, fd->fd_base + AIE_START_REG);
> + }
> + }
> +}
> +
next prev parent reply other threads:[~2024-12-26 3:55 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-25 9:00 [PATCH v3 0/4] Add AIE Driver bo.kong
2024-12-25 9:00 ` [PATCH v3 1/4] arm64: dts: mt8188: add aie node bo.kong
2024-12-25 9:00 ` [PATCH v3 2/4] media: dt-bindings: add MT8188 AIE bo.kong
2024-12-25 10:29 ` Rob Herring (Arm)
2024-12-25 11:28 ` Krzysztof Kozlowski
2024-12-26 3:41 ` CK Hu (胡俊光)
2024-12-25 9:00 ` [PATCH v3 3/4] media: mediatek: add MT8188 AIE driver bo.kong
2024-12-25 11:35 ` Krzysztof Kozlowski
2024-12-26 3:53 ` CK Hu (胡俊光) [this message]
2024-12-26 5:20 ` CK Hu (胡俊光)
2024-12-26 5:36 ` CK Hu (胡俊光)
2024-12-26 6:09 ` CK Hu (胡俊光)
2024-12-26 6:50 ` CK Hu (胡俊光)
2024-12-26 7:38 ` CK Hu (胡俊光)
2024-12-27 3:23 ` CK Hu (胡俊光)
2024-12-27 3:54 ` CK Hu (胡俊光)
2024-12-27 5:56 ` CK Hu (胡俊光)
2024-12-27 6:05 ` CK Hu (胡俊光)
2024-12-31 7:45 ` Krzysztof Kozlowski
2024-12-31 7:57 ` CK Hu (胡俊光)
2024-12-31 8:07 ` Krzysztof Kozlowski
2024-12-31 8:13 ` CK Hu (胡俊光)
2024-12-30 7:39 ` CK Hu (胡俊光)
2025-01-07 15:32 ` AngeloGioacchino Del Regno
2024-12-25 9:00 ` [PATCH v3 4/4] uapi: linux: add MT8188 AIE bo.kong
2024-12-26 6:36 ` CK Hu (胡俊光)
2024-12-31 6:55 ` CK Hu (胡俊光)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=95345df12095e976fedfcfcc6aac77f5d6a2d2b8.camel@mediatek.com \
--to=ck.hu@mediatek.com \
--cc=Bo.Kong@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-media@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=mchehab@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.