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Fri, 25 Mar 2022 00:16:37 -0700 Message-ID: <959e037c-d7a3-53a7-ba8c-e8a5a547f2fa@xilinx.com> Date: Fri, 25 Mar 2022 08:16:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH] arm64: zynqmp: enable the PMUFW watchdog Content-Language: en-US To: "Jorge Ramirez-Ortiz, Foundries" , Michal Simek CC: , , , , , References: <20220323140458.1087767-1-jorge@foundries.io> <41d78294-8f0d-3b08-e614-f61425a38751@xilinx.com> <20220324210311.GA1801385@trex> From: Michal Simek In-Reply-To: <20220324210311.GA1801385@trex> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fb123db6-70dd-4785-7e09-08da0e2f6708 X-MS-TrafficTypeDiagnostic: BYAPR02MB5989:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(8676002)(6666004)(508600001)(966005)(2616005)(70586007)(316002)(53546011)(83380400001)(36860700001)(31686004)(36756003)(426003)(31696002)(9786002)(8936002)(2906002)(70206006)(4326008)(5660300002)(7636003)(44832011)(82310400004)(47076005)(26005)(110136005)(356005)(54906003)(40460700003)(186003)(336012)(50156003)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2022 07:16:38.0270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb123db6-70dd-4785-7e09-08da0e2f6708 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT025.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5989 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 3/24/22 22:03, Jorge Ramirez-Ortiz, Foundries wrote: > On 24/03/22, Michal Simek wrote: >> >> >> On 3/23/22 15:04, Jorge Ramirez-Ortiz wrote: >>> From 528b3117a36b7b4eea1839afbea7191d60638b0c Mon Sep 17 00:00:00 2001 >>> From: Jorge Ramirez-Ortiz >>> Date: Wed, 23 Mar 2022 14:41:15 +0100 >>> Subject: [PATCH] arm64: zynqmp: enable the PMUFW watchdog >>> >>> If the PMUFW was built with support for the CSU watchdog we must let the >>> firmware know that it can be started. >>> >>> We do this by faking the FSBL done state. >>> >>> Reference code in PMUFW: >>> https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_apps/zynqmp_pmufw/src/xpfw_mod_common.c#L36 >>> >>> It needs this fix on the PMUFW >>> https://github.com/Xilinx/embeddedsw/pull/190 >> >> >> /* FSBL might not be running anywhere - i.e: SPL boots PMUFW */ >> >> SPL doesn't boot PMUFW. It is the first firmware in BOOT.BIN which is loaded >> by bootrom to PMU. It means comment is not correct. >> FSBL or SPL just sending PMU configuration object to PMUFW. > > yeah I guess it depends what you mean by boot - unless SPL configures it, it > wont really boot to a functional state. > > but anyway ok, will change. > > >> >> >> >> >>> >>> Signed-off-by: Jorge Ramirez-Ortiz >>> --- >>> arch/arm/mach-zynqmp/include/mach/hardware.h | 5 ++++- >>> board/xilinx/zynqmp/zynqmp.c | 4 ++++ >>> 2 files changed, 8 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h >>> index a70d6d611b..24c3ef3d7d 100644 >>> --- a/arch/arm/mach-zynqmp/include/mach/hardware.h >>> +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h >>> @@ -174,8 +174,11 @@ struct csu_regs { >>> #define ZYNQMP_PMU_BASEADDR 0xFFD80000 >>> +#define FSBL_COMPLETION 0x1 >>> + >>> struct pmu_regs { >>> - u32 reserved[18]; >>> + u32 reserved[17]; >>> + u32 gen_storage5; /* 0x44 */ >>> u32 gen_storage6; /* 0x48 */ >>> }; >>> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c >>> index 70b3c81f12..c88c5fb8ea 100644 >>> --- a/board/xilinx/zynqmp/zynqmp.c >>> +++ b/board/xilinx/zynqmp/zynqmp.c >>> @@ -419,6 +419,10 @@ int board_init(void) >>> zynqmp_pm_cfg_obj_size); >>> printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); >>> + /* fake FSBL completion to start the PMUFW watchdog when enabled */ >>> + writel(readl(&pmu_base->gen_storage5) | FSBL_COMPLETION, >>> + &pmu_base->gen_storage5); >> >> I look at the code in FSBL and it set it up XFsbl_HandoffExit which is at >> the end of FSBL. It means this should be setup in SPL not in U-Boot proper. > > not sure what you mean. This piece of code I am posting only executes in SPL, > doesn it? ah. ok. Then fine. M