From: Stephen Boyd <sboyd@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>
Cc: linux-renesas-soc@vger.kernel.org
<linux-renesas-soc@vger.kernel.org>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
biju.das.au <biju.das.au@gmail.com>,
linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>
Subject: RE: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock
Date: Thu, 20 Mar 2025 14:56:56 -0700 [thread overview]
Message-ID: <983e0e616d62f236dcbc3eecbeab5ab4.sboyd@kernel.org> (raw)
In-Reply-To: <TY3PR01MB11346D2881A8CC9C3019C978386D22@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Quoting Biju Das (2025-03-14 00:18:33)
> Hi Stephen,
>
> > -----Original Message-----
> > From: Biju Das
> > Sent: 07 March 2025 07:02
> > Subject: RE: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock
> >
> > Hi Stephen,
> >
> > > -----Original Message-----
> > > From: Stephen Boyd <sboyd@kernel.org>
> > > Sent: 06 March 2025 22:37
> > > Subject: RE: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for
> > > coupled clock
> > >
> > > Quoting Biju Das (2025-03-06 02:10:50)
> > > > > From: Stephen Boyd <sboyd@kernel.org> Quoting Biju Das (2025-03-03
> > > > > 03:04:19)
> > > > > > The spi and spix2 clk share same bit for clock gating. Add
> > > > > > support for coupled clock with checking the monitor bit for both the clocks.
> > > > >
> > > > > Could you add an intermediate parent clk of both spi and spix2
> > > > > that only handles the enable bit for clock gating? Then the enable
> > > > > count handling would be in the core
> > > clk code.
> > > >
> > > > The parent clock rate of spi and spix2 are different. If we use an
> > > > intermediate parent clk, What clk rate the parent will use??
> > >
> > > Alright, got it. Does the consumer care about the difference between the two clks for the gating
> > part?
> >
> > Although gating bit is same, for some reason their monitor bit is different. So, to confirm clk on
> > status we need to check respective monitor bits. Parallelly, I will check with hardware team, does it
> > need to monitor both these bits??
>
> According to hardware team, the spix2 clock is twice the frequency of the spi clock, and the clock ON/OFF
> period displayed for each bit in the monitor register varies slightly due to the difference in frequency.
>
> So to check the status after changing the clock ON/OFF register setting,
> please check the two monitor register bits together
>
That answers the hardware side of the question. Why does software need
to care that they're two different things vs. one clk?
next prev parent reply other threads:[~2025-03-20 21:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-03 11:04 [PATCH 0/4] Add RZ/G3E XSPI clocks Biju Das
2025-03-03 11:04 ` [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock Biju Das
2025-03-05 23:16 ` Stephen Boyd
2025-03-06 10:10 ` Biju Das
2025-03-06 22:36 ` Stephen Boyd
[not found] ` <TY3PR01MB113469E04E10E3D14FB3F69F186D52@TY3PR01MB11346.jpnprd01.prod.outlook.com>
2025-03-14 7:18 ` Biju Das
2025-03-20 21:56 ` Stephen Boyd [this message]
2025-03-21 14:21 ` Biju Das
2025-03-24 23:48 ` Stephen Boyd
2025-03-25 12:22 ` Biju Das
2025-03-26 15:17 ` Biju Das
2025-03-03 11:04 ` [PATCH 2/4] clk: renesas: rzv2h-cpg: Add support for static dividers Biju Das
2025-03-03 11:04 ` [PATCH 3/4] clk: renesas: r9a09g047: Add support for xspi mux and divider Biju Das
2025-03-03 11:04 ` [PATCH 4/4] clk: renesas: r9a09g047: Add XSPI clock/reset Biju Das
2025-03-06 14:44 ` Geert Uytterhoeven
2025-03-20 9:56 ` Biju Das
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