From: Reinette Chatre <reinette.chatre@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: tglx@linutronix.de, fenghua.yu@intel.com, tony.luck@intel.com,
kuo-lang.tseng@intel.com, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 01/10] x86/CPU: Expose if cache is inclusive of lower level caches
Date: Tue, 6 Aug 2019 14:16:10 -0700 [thread overview]
Message-ID: <98eeaa53-d100-28ff-0b68-ba57e0ea90fb@intel.com> (raw)
In-Reply-To: <20190806204054.GD4698@zn.tnic>
Hi Borislav,
On 8/6/2019 1:40 PM, Borislav Petkov wrote:
> On Tue, Aug 06, 2019 at 01:22:22PM -0700, Reinette Chatre wrote:
>> ... because some platforms differ in which SKUs support cache
>> pseudo-locking. On these platforms only the SKUs with inclusive cache
>> support cache pseudo-locking, thus the additional check.
>
> Ok, so it sounds to me like that check in get_prefetch_disable_bits()
> should be extended (and maybe renamed) to check for cache inclusivity
> too, in order to know which platforms support cache pseudo-locking.
Indeed. As you pointed out this would be same system-wide and the check
thus need not be delayed until it is known which cache is being
pseudo-locked.
> I'd leave it to tglx to say how we should mirror cache inclusivity in
> cpuinfo_x86: whether a synthetic X86_FEATURE bit or cache the respective
> CPUID words which state whether L2/L3 is inclusive...
Thank you very much. I appreciate your guidance here.
Reinette
next prev parent reply other threads:[~2019-08-06 21:16 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 17:29 [PATCH V2 00/10] x86/CPU and x86/resctrl: Support pseudo-lock regions spanning L2 and L3 cache Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 01/10] x86/CPU: Expose if cache is inclusive of lower level caches Reinette Chatre
2019-08-02 18:03 ` Borislav Petkov
2019-08-02 20:11 ` Reinette Chatre
2019-08-03 9:44 ` Borislav Petkov
2019-08-05 17:57 ` Reinette Chatre
2019-08-06 15:57 ` Borislav Petkov
2019-08-06 16:55 ` Reinette Chatre
2019-08-06 17:33 ` Borislav Petkov
2019-08-06 18:13 ` Reinette Chatre
2019-08-06 18:33 ` Borislav Petkov
2019-08-06 18:53 ` Reinette Chatre
2019-08-06 19:16 ` Borislav Petkov
2019-08-06 20:22 ` Reinette Chatre
2019-08-06 20:40 ` Borislav Petkov
2019-08-06 21:16 ` Reinette Chatre [this message]
2019-08-08 8:08 ` Borislav Petkov
2019-08-08 8:13 ` Borislav Petkov
2019-08-08 20:08 ` Reinette Chatre
2019-08-09 7:33 ` Borislav Petkov
2019-08-09 16:18 ` Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 02/10] x86/resctrl: Remove unnecessary size compute Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 03/10] x86/resctrl: Constrain C-states during pseudo-lock region init Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 04/10] x86/resctrl: Set cache line size using new utility Reinette Chatre
2019-08-05 15:57 ` Borislav Petkov
2019-07-30 17:29 ` [PATCH V2 05/10] x86/resctrl: Associate pseudo-locked region's cache instance by id Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 06/10] x86/resctrl: Introduce utility to return pseudo-locked cache portion Reinette Chatre
2019-08-05 16:07 ` Borislav Petkov
2019-07-30 17:29 ` [PATCH V2 07/10] x86/resctrl: Remove unnecessary pointer to pseudo-locked region Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 08/10] x86/resctrl: Support pseudo-lock regions spanning resources Reinette Chatre
2019-08-07 9:18 ` Borislav Petkov
2019-08-07 19:07 ` Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 09/10] x86/resctrl: Pseudo-lock portions of multiple resources Reinette Chatre
2019-08-07 15:25 ` Borislav Petkov
2019-08-07 19:23 ` Reinette Chatre
2019-08-08 8:44 ` Borislav Petkov
2019-08-08 20:13 ` Reinette Chatre
2019-08-09 7:38 ` Borislav Petkov
2019-08-09 16:20 ` Reinette Chatre
2019-07-30 17:29 ` [PATCH V2 10/10] x86/resctrl: Only pseudo-lock L3 cache when inclusive Reinette Chatre
2019-07-30 20:00 ` [PATCH V2 00/10] x86/CPU and x86/resctrl: Support pseudo-lock regions spanning L2 and L3 cache Thomas Gleixner
2019-07-30 20:10 ` Reinette Chatre
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