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From: Michael Walle <mwalle@kernel.org>
To: Flavio Suligoi <f.suligoi@asem.it>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>,
	Pratyush Yadav <pratyush@kernel.org>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] mtd: spi-nor: everspin: add em004lxb entry
Date: Thu, 01 Feb 2024 14:47:34 +0100	[thread overview]
Message-ID: <9a22148dd786dd1c37f10412b574aae8@kernel.org> (raw)
In-Reply-To: <20240201131710.797505-2-f.suligoi@asem.it>

Hi,

> Add the Everspin EM0004LXB 4Mb (512KB) Industrial STT-MRAM Persistent
> Memory.

Out of curiosity, what is your use case here? Usually, I push back on
this small MRAM devices in SPI-NOR in favor of the at25 driver. But
this datasheet lists octal dtr with 200mhz, which seems a bit ridiculous
for 512kB. The at25 driver only supports single bit SPI of course.

I'm not sure in which mode you are using this device, though. The DS
shows a non-volatile configuration register (Table 10, offset 0) and
it's default value is single bit SPI.

> This device is JEDEC compatible (JESD251 and JESD251-1), but it is not
> able to provide SFDP information.
> 
> Link: https://www.everspin.com/file/158244/download

No newline.

> Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
> ---
>  drivers/mtd/spi-nor/everspin.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/everspin.c 
> b/drivers/mtd/spi-nor/everspin.c
> index 5f321e24ae7d..4741930ce9a8 100644
> --- a/drivers/mtd/spi-nor/everspin.c
> +++ b/drivers/mtd/spi-nor/everspin.c
> @@ -31,6 +31,14 @@ static const struct flash_info everspin_nor_parts[] 
> = {
>  		.size = SZ_512K,
>  		.sector_size = SZ_512K,
>  		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
> +	}, {
> +		.id = SNOR_ID(0x6b, 0xbb, 0x13),
> +		.name = "em004lxb",

No name. We prefer to only have the ID for parts which has JEDED IDs.

> +		.size = SZ_512K,
> +		.sector_size = SZ_512K,

This should probably be removed (and then default to the 64k erase
size).

> +		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR | SPI_NOR_HAS_LOCK |

Don't use SPI_NOR_NO_ERASE for new devices. Eventually, I like to get 
rid of
this flag. This device is emulating the erase instruction, so it should 
work
without.

SPI_NOR_NO_FR is wrong here. The DS says it supports fast read.

Please also have a look at [1] for the required tests.

-michael

> +			 SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6,
> +		.no_sfdp_flags = SPI_NOR_SKIP_SFDP,
>  	}
>  };

[1] https://docs.kernel.org/driver-api/mtd/spi-nor.html

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <mwalle@kernel.org>
To: Flavio Suligoi <f.suligoi@asem.it>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>,
	Pratyush Yadav <pratyush@kernel.org>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] mtd: spi-nor: everspin: add em004lxb entry
Date: Thu, 01 Feb 2024 14:47:34 +0100	[thread overview]
Message-ID: <9a22148dd786dd1c37f10412b574aae8@kernel.org> (raw)
In-Reply-To: <20240201131710.797505-2-f.suligoi@asem.it>

Hi,

> Add the Everspin EM0004LXB 4Mb (512KB) Industrial STT-MRAM Persistent
> Memory.

Out of curiosity, what is your use case here? Usually, I push back on
this small MRAM devices in SPI-NOR in favor of the at25 driver. But
this datasheet lists octal dtr with 200mhz, which seems a bit ridiculous
for 512kB. The at25 driver only supports single bit SPI of course.

I'm not sure in which mode you are using this device, though. The DS
shows a non-volatile configuration register (Table 10, offset 0) and
it's default value is single bit SPI.

> This device is JEDEC compatible (JESD251 and JESD251-1), but it is not
> able to provide SFDP information.
> 
> Link: https://www.everspin.com/file/158244/download

No newline.

> Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
> ---
>  drivers/mtd/spi-nor/everspin.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/everspin.c 
> b/drivers/mtd/spi-nor/everspin.c
> index 5f321e24ae7d..4741930ce9a8 100644
> --- a/drivers/mtd/spi-nor/everspin.c
> +++ b/drivers/mtd/spi-nor/everspin.c
> @@ -31,6 +31,14 @@ static const struct flash_info everspin_nor_parts[] 
> = {
>  		.size = SZ_512K,
>  		.sector_size = SZ_512K,
>  		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
> +	}, {
> +		.id = SNOR_ID(0x6b, 0xbb, 0x13),
> +		.name = "em004lxb",

No name. We prefer to only have the ID for parts which has JEDED IDs.

> +		.size = SZ_512K,
> +		.sector_size = SZ_512K,

This should probably be removed (and then default to the 64k erase
size).

> +		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR | SPI_NOR_HAS_LOCK |

Don't use SPI_NOR_NO_ERASE for new devices. Eventually, I like to get 
rid of
this flag. This device is emulating the erase instruction, so it should 
work
without.

SPI_NOR_NO_FR is wrong here. The DS says it supports fast read.

Please also have a look at [1] for the required tests.

-michael

> +			 SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6,
> +		.no_sfdp_flags = SPI_NOR_SKIP_SFDP,
>  	}
>  };

[1] https://docs.kernel.org/driver-api/mtd/spi-nor.html

  reply	other threads:[~2024-02-01 13:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-01 13:17 [PATCH 0/1] mtd: spi-nor: everspin: add em004lxb entry Flavio Suligoi
2024-02-01 13:17 ` Flavio Suligoi
2024-02-01 13:17 ` [PATCH 1/1] " Flavio Suligoi
2024-02-01 13:17   ` Flavio Suligoi
2024-02-01 13:47   ` Michael Walle [this message]
2024-02-01 13:47     ` Michael Walle
2024-02-01 14:07     ` Flavio Suligoi
2024-02-01 14:07       ` Flavio Suligoi
  -- strict thread matches above, loose matches on Subject: below --
2024-04-05 10:01 [PATCH 0/1] " Flavio Suligoi
2024-04-05 10:01 ` [PATCH 1/1] " Flavio Suligoi
2024-04-05 10:01   ` Flavio Suligoi
2024-04-05 13:03   ` Francesco Dolcini
2024-04-05 13:03     ` Francesco Dolcini
2024-04-05 14:41   ` Michael Walle
2024-04-05 14:41     ` Michael Walle

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