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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by DM2PEPF00003FC3.mail.protection.outlook.com (10.167.23.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Mon, 27 Apr 2026 04:34:58 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Sun, 26 Apr 2026 23:34:58 -0500 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Sun, 26 Apr 2026 23:34:58 -0500 Received: from [10.252.198.192] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Sun, 26 Apr 2026 23:34:55 -0500 Message-ID: <9a9f712e-5f01-4652-9901-93cf3bdeef47@amd.com> Date: Mon, 27 Apr 2026 10:04:53 +0530 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers From: "Shukla, Manali" To: , CC: , , , , , , , , References: <20260204074452.55453-1-manali.shukla@amd.com> <0a9b715c-0476-469d-a09e-b56cb9f41455@amd.com> Content-Language: en-US In-Reply-To: <0a9b715c-0476-469d-a09e-b56cb9f41455@amd.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8e6g5ZSc8eC1Cs7950JquZa7uXBx7fl204RxBOtBj1JqfocaiES5uC0rj+ozEifTsGnQNQgwQ2ll+uWKip/XONRZJ7Z12UXv0WMluZNZM0HilB6csOs2DWqRt7Q0DagT8RlS/pzEuG0iDjPcG+qI/Fr6ps/dSi1yoU3Rq4FFh7L4zTL1EcT4eFQQjQIrcsonjuyMRILIK19WgDlJujRcKRyIchUEZdK63/W2CJTpZd/pISbK67xAeYLOH4mCMmHgI7i/9TElNtSsSTh1KvmFD4/gpDx7Bo2Q2gnJQ3dk39YJccARzX4YJ/9YPihTpHphHfQ+sl2DEXAf92GvmvBqPyV1TEIbjqqatEghRIkaKMqluplSwBhZOdComJ71JACas4uwNm2Y2WdvH/FiyBdbYnbPFp7fWBvD7khJ28+Qsg9yBbcn5Lz3MqSnYKJ7CjqW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 04:34:58.4695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6c686f2-146a-4c6e-5813-08dea41656c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4335 On 3/10/2026 11:47 AM, Manali Shukla wrote: > On 2/4/2026 1:14 PM, Manali Shukla wrote: >> Add support for AMD's Extended APIC registers, which reside in a 4KB >> APIC page instead of the legacy 1KB APIC register space. Extended LVT >> registers (offsets 0x500-0x530) provide additional interrupt vectors >> for features like Instruction Based Sampling (IBS). >> >> Introduce KVM_CAP_LAPIC2 to allow userspace to opt into the full 4KB >> APIC register space. The capability uses a bitmask to support different >> APIC extensions: >> >> KVM_LAPIC2_DEFAULT: 4KB APIC register space (common foundation) >> KVM_LAPIC2_AMD_DEFAULT: Extended LVT registers (AMD-specific) >> >> Add KVM_GET/SET_LAPIC2 ioctls that operate on a 4KB APIC register space >> accommodate extended registers. Legacy KVM_GET/SET_LAPIC continue to >> work for backward compatibility. >> >> Emulate extended APIC registers (APIC_EFEAT, APIC_ECTRL, APIC_EILVTn) >> when the guest has X86_FEATURE_EXTAPIC and userspace enables >> KVM_CAP_LAPIC2. Current AMD processors support four extended LVT >> entries, future processors may support up to 255. >> >> Integrate with AVIC to accelerate extended LVT MSR access when >> AVIC_EXTLVT is supported. Reads are accelerated without VM-exits; >> writes trigger trap-style VM-exits. >> >> Tested on AMD hardware with Extapic support: >> - Extended APIC register read/write emulation and AVIC acceleration >> with IBS driver running on the guest >> - VM migration with extended APIC state and without extended APIC state >> - Backward compatibility check: >> Fallback to legacy IOCTLs when KVM_CAP_LAPIC2 capability is not enabled >> >> Equivalent Qemu changes can be found at: >> https://github.com/AMDESE/qemu/tree/extlvt_v1 >> >> Patches are prepared on kvm-x86/next (003f68c79227). >> >> Manali Shukla (7): >> KVM: x86: Refactor APIC register mask handling to support extended >> APIC registers >> x86/apic: Add helper to get maximum number of Extended LVT registers >> KVM: SVM: Set kvm_caps.has_extapic when CPU supports Extended APIC >> KVM: x86: Introduce KVM_CAP_LAPIC2 for 4KB APIC register space support >> KVM: x86: Refactor APIC state get/set to accept variable-sized buffers >> KVM: Add KVM_GET_LAPIC2 and KVM_SET_LAPIC2 for extended APIC >> KVM: SVM: Add AVIC support for extended LVT MSRs >> >> Santosh Shukla (2): >> KVM: x86: Emulate Extended LVT registers for AMD guests >> x86/cpufeatures: Add CPUID feature bit for Extended LVT AVIC >> acceleration >> >> Documentation/virt/kvm/api.rst | 75 +++++++++++++ >> arch/x86/include/asm/apic.h | 1 + >> arch/x86/include/asm/apicdef.h | 18 +++ >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/include/asm/kvm_host.h | 12 ++ >> arch/x86/include/uapi/asm/kvm.h | 5 + >> arch/x86/kernel/apic/apic.c | 17 +++ >> arch/x86/kvm/cpuid.c | 10 +- >> arch/x86/kvm/lapic.c | 169 ++++++++++++++++++++--------- >> arch/x86/kvm/lapic.h | 14 ++- >> arch/x86/kvm/svm/avic.c | 14 +++ >> arch/x86/kvm/svm/svm.c | 3 + >> arch/x86/kvm/vmx/vmx.c | 10 +- >> arch/x86/kvm/x86.c | 93 +++++++++++++++- >> arch/x86/kvm/x86.h | 2 + >> include/uapi/linux/kvm.h | 7 ++ >> 16 files changed, 390 insertions(+), 61 deletions(-) >> > > A Gentle reminder to review. > > -Manali > A Gentle reminder to review. -Manali