All of lore.kernel.org
 help / color / mirror / Atom feed
From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
	"Baptiste Le Duc" <baptiste.le-duc@vates.tech>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Connor Davis" <connojdavis@gmail.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Anthony PERARD" <anthony.perard@vates.tech>,
	"Michal Orzel" <michal.orzel@amd.com>,
	"Julien Grall" <julien@xen.org>,
	"Roger Pau Monné" <roger@xenproject.org>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v7 04/20] xen/riscv: introduce guest riscv,isa string
Date: Thu, 13 Aug 2026 17:37:14 +0200	[thread overview]
Message-ID: <9abc0091-43e5-475e-ae61-697f480dda5e@gmail.com> (raw)
In-Reply-To: <3bb59f64-7ff1-4bdc-b951-cfb78671e8f9@suse.com>



On 8/13/26 9:19 AM, Jan Beulich wrote:
> On 04.08.2026 17:47, Oleksii Kurochko wrote:
>> @@ -120,29 +148,30 @@ static int __init dt_get_cpuid_from_node(const struct dt_device_node *cpu,
>>    * and strncmp() is used in match_isa_ext() to compare extension names instead
>>    * of strncasecmp().
>>    */
>> -const struct riscv_isa_ext_data __initconst riscv_isa_ext[] = {
>> -    RISCV_ISA_EXT_DATA(i),
>> -    RISCV_ISA_EXT_DATA(m),
>> -    RISCV_ISA_EXT_DATA(a),
>> -    RISCV_ISA_EXT_DATA(f),
>> -    RISCV_ISA_EXT_DATA(d),
>> -    RISCV_ISA_EXT_DATA(q),
>> -    RISCV_ISA_EXT_DATA(c),
>> -    RISCV_ISA_EXT_DATA(h),
>> -    RISCV_ISA_EXT_DATA(zicntr),
>> -    RISCV_ISA_EXT_DATA(zicsr),
>> -    RISCV_ISA_EXT_DATA(zifencei),
>> -    RISCV_ISA_EXT_DATA(zihintpause),
>> -    RISCV_ISA_EXT_DATA(zihpm),
>> -    RISCV_ISA_EXT_DATA(zba),
>> -    RISCV_ISA_EXT_DATA(zbb),
>> -    RISCV_ISA_EXT_DATA(zbs),
>> -    RISCV_ISA_EXT_DATA(smaia),
>> -    RISCV_ISA_EXT_DATA(smstateen),
>> -    RISCV_ISA_EXT_DATA(ssaia),
>> -    RISCV_ISA_EXT_DATA(sstc),
>> -    RISCV_ISA_EXT_DATA(svade),
>> -    RISCV_ISA_EXT_DATA(svpbmt),
>> +static const struct riscv_isa_ext_entry __initconstrel riscv_isa_ext[] = {
>> +    RISCV_ISA_EXT_ENTRY(i,            true),
>> +    RISCV_ISA_EXT_ENTRY(m,            true),
>> +    RISCV_ISA_EXT_ENTRY(a,            true),
>> +    RISCV_ISA_EXT_ENTRY(f,            false),
>> +    RISCV_ISA_EXT_ENTRY(d,            false),
>> +    RISCV_ISA_EXT_ENTRY(q,            false),
>> +    RISCV_ISA_EXT_ENTRY(c,            true),
>> +    RISCV_ISA_EXT_ENTRY(v,            false),
>> +    RISCV_ISA_EXT_ENTRY(h,            false),
>> +    RISCV_ISA_EXT_ENTRY(zicntr,       true),
>> +    RISCV_ISA_EXT_ENTRY(zicsr,        true),
>> +    RISCV_ISA_EXT_ENTRY(zifencei,     true),
>> +    RISCV_ISA_EXT_ENTRY(zihintpause,  true),
>> +    RISCV_ISA_EXT_ENTRY(zihpm,        true),
>> +    RISCV_ISA_EXT_ENTRY(zba,          true),
>> +    RISCV_ISA_EXT_ENTRY(zbb,          true),
>> +    RISCV_ISA_EXT_ENTRY(zbs,          true),
>> +    RISCV_ISA_EXT_ENTRY(smaia,        true),
>> +    RISCV_ISA_EXT_ENTRY(smstateen,    true),
>> +    RISCV_ISA_EXT_ENTRY(ssaia,        true),
>> +    RISCV_ISA_EXT_ENTRY(sstc,         false),
>> +    RISCV_ISA_EXT_ENTRY(svade,        false),
>> +    RISCV_ISA_EXT_ENTRY(svpbmt,       false),
>>   };
> 
> Just as an independent, up front remark after having looked at patch 16/17 of
> the other series: Is a mere boolean going to suffice in the longer run? I could
> see some extensions wanting exposing to only RV32 or only RV64 guests. E.g.
> Zilsd is RV32-only, while Zqinx quite likely would want restricting to RV64.

Good point generally.

Right now the distinction can't be observed: RV32 isn't buildable 
(#error "RV32 isn't supported" in asm/config.h), and guest XLEN is 
hard-wired to host XLEN — build_guest_isa_str() emits the rv32/rv64 
prefix from the Kconfig symbol, and riscv_isa_parse_string() rejects a 
host ISA string of the other width.

On top of that, extensions with an architectural XLEN restriction are 
already filtered out for free: compute_guest_isa() masks the table 
against the host bitmap, so an RV32-only extension like Zilsd can't have 
its bit set on an RV64 build regardless of what the table says. The 
boolean only ever subtracts from what the host actually reports.

That leaves purely policy-driven per-XLEN restrictions — e.g. exposing 
Zqinx to RV64 guests but not RV32 ones, since Zqinx is architecturally 
defined for both. Those only become meaningful once guest XLEN can 
differ from host XLEN (i.e. hstatus.VSXL support), and at that point the 
shared guest_isa bitmap has to become per-domain as well, as the comment 
above it already notes.

So I'd rather keep the plain bool for now and widen it to a flags field 
when there's an actual case; it's a mechanical change to the struct, the 
macro and the single test in compute_guest_isa(), all local to 
cpufeature.c. I can add a comment stating the "guest XLEN == host XLEN" 
assumption so the reason is on record. If you'd prefer it as flags from 
the start I don't mind doing it now either. I just don't have a way to 
give either value a meaning yet. So if to do that now I would suggest 
the following:


+/*
+ * Which guests an extension may be handed out to, by guest XLEN.
+ *
+ * These flags express Xen's policy, not the ISA's rules: extensions which
+ * are architecturally tied to one XLEN (Zilsd on RV32, say) need no 
special
+ * treatment here, as they can only ever appear in the "riscv,isa" of a 
host
+ * of that XLEN, and guest_isa is masked against the host ISA bitmap 
anyway.
+ * They are only of use for extensions Xen chooses not to expose to 
guests of
+ * a given width despite the hardware implementing them.
+ */
+#define RISCV_ISA_EXT_GUEST_NONE 0
+#define RISCV_ISA_EXT_GUEST_RV32 (1U << 0)
+#define RISCV_ISA_EXT_GUEST_RV64 (1U << 1)
+#define RISCV_ISA_EXT_GUEST_ANY  (RISCV_ISA_EXT_GUEST_RV32 | \
+                                  RISCV_ISA_EXT_GUEST_RV64)
+
+/*
+ * Guests are of the same width as Xen itself for the time being; once 
guest
+ * XLEN can differ from host XLEN (hstatus.VSXL), this becomes a per-domain
+ * property, just as guest_isa below does.
+ */
+#if defined(CONFIG_RISCV_32)
+#define RISCV_ISA_EXT_GUEST_XLEN RISCV_ISA_EXT_GUEST_RV32
+#elif defined(CONFIG_RISCV_64)
+#define RISCV_ISA_EXT_GUEST_XLEN RISCV_ISA_EXT_GUEST_RV64
+#else
+# error "Unsupported RISC-V bitness"
+#endif
+
  struct riscv_isa_ext_entry {
      unsigned int id;
      const char *name;
-    bool guest_supported;
+    unsigned int guest_flags;
  };

-#define RISCV_ISA_EXT_ENTRY(ext_name, guest_supp)       \
+#define RISCV_ISA_EXT_ENTRY(ext_name, guest_flgs)       \
  {                                                       \
-    .id              = RISCV_ISA_EXT_ ## ext_name,      \
-    .name            = #ext_name,                       \
-    .guest_supported = guest_supp,                      \
+    .id          = RISCV_ISA_EXT_ ## ext_name,          \
+    .name        = #ext_name,                           \
+    .guest_flags = guest_flgs,                          \
  }

  /* Host ISA bitmap */
@@ -149,29 +178,29 @@ static int __init dt_get_cpuid_from_node(const 
struct dt_device_node *cpu,
   * of strncasecmp().
   */
  static const struct riscv_isa_ext_entry __initconstrel riscv_isa_ext[] = {
-    RISCV_ISA_EXT_ENTRY(i,            true),
-    RISCV_ISA_EXT_ENTRY(m,            true),
-    RISCV_ISA_EXT_ENTRY(a,            true),
-    RISCV_ISA_EXT_ENTRY(f,            false),
-    RISCV_ISA_EXT_ENTRY(d,            false),
-    RISCV_ISA_EXT_ENTRY(q,            false),
-    RISCV_ISA_EXT_ENTRY(c,            true),
-    RISCV_ISA_EXT_ENTRY(v,            false),
-    RISCV_ISA_EXT_ENTRY(h,            false),
-    RISCV_ISA_EXT_ENTRY(zicntr,       true),
-    RISCV_ISA_EXT_ENTRY(zicsr,        true),
-    RISCV_ISA_EXT_ENTRY(zifencei,     true),
-    RISCV_ISA_EXT_ENTRY(zihintpause,  true),
-    RISCV_ISA_EXT_ENTRY(zihpm,        true),
-    RISCV_ISA_EXT_ENTRY(zba,          true),
-    RISCV_ISA_EXT_ENTRY(zbb,          true),
-    RISCV_ISA_EXT_ENTRY(zbs,          true),
-    RISCV_ISA_EXT_ENTRY(smaia,        true),
-    RISCV_ISA_EXT_ENTRY(smstateen,    true),
-    RISCV_ISA_EXT_ENTRY(ssaia,        true),
-    RISCV_ISA_EXT_ENTRY(sstc,         false),
-    RISCV_ISA_EXT_ENTRY(svade,        false),
-    RISCV_ISA_EXT_ENTRY(svpbmt,       false),
+    RISCV_ISA_EXT_ENTRY(i,            RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(m,            RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(a,            RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(f,            RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(d,            RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(q,            RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(c,            RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(v,            RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(h,            RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(zicntr,       RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zicsr,        RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zifencei,     RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zihintpause,  RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zihpm,        RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zba,          RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zbb,          RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(zbs,          RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(smaia,        RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(smstateen,    RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(ssaia,        RISCV_ISA_EXT_GUEST_ANY),
+    RISCV_ISA_EXT_ENTRY(sstc,         RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(svade,        RISCV_ISA_EXT_GUEST_NONE),
+    RISCV_ISA_EXT_ENTRY(svpbmt,       RISCV_ISA_EXT_GUEST_NONE),
  };

  static const struct riscv_isa_ext_data __initconst 
required_extensions[] = {
@@ -572,7 +601,7 @@ static void __init compute_guest_isa(void)
      {
          const struct riscv_isa_ext_entry *ext = &riscv_isa_ext[i];

-        if ( ext->guest_supported &&
+        if ( (ext->guest_flags & RISCV_ISA_EXT_GUEST_XLEN) &&
               riscv_isa_extension_available(NULL, ext->id) )
              __set_bit(ext->id, guest_isa);
      }

Will you be okay with such changes or it could be postponed to a time 
when it will be really needed?

~ Oleksii


  reply	other threads:[~2026-08-13 15:37 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04 15:47 [PATCH v7 00/20] Introduce enablemenant of dom0less Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 01/20] xen: introduce CONFIG_HAS_SHARED_INFO for archs without a shared page Oleksii Kurochko
2026-08-13 14:54   ` Jan Beulich
2026-08-13 17:03     ` Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 02/20] xen/dom0less: turn max_init_domid into a common variable Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 03/20] xen/riscv: Implement construct_domain() Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 04/20] xen/riscv: introduce guest riscv,isa string Oleksii Kurochko
2026-08-13  7:19   ` Jan Beulich
2026-08-13 15:37     ` Oleksii Kurochko [this message]
2026-08-13 15:43       ` Jan Beulich
2026-08-13 16:00         ` Oleksii Kurochko
2026-08-13 15:35   ` Jan Beulich
2026-08-04 15:47 ` [PATCH v7 05/20] xen/riscv: implement make_cpus_node() Oleksii Kurochko
2026-08-13 15:37   ` Jan Beulich
2026-08-04 15:47 ` [PATCH v7 06/20] xen/riscv: implement make_timer_node() Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 07/20] xen/riscv: implement make_arch_nodes() Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 08/20] xen/riscv: introduce init interrupt controller operations Oleksii Kurochko
2026-08-04 15:47 ` [PATCH v7 09/20] xen/riscv: implement make_intc_domU_node() Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 10/20] xen/riscv: introduce aia_init() and aia_usable() Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 11/20] xen/riscv: introduce per-vCPU IMSIC state Oleksii Kurochko
2026-08-13 15:39   ` Oleksii Kurochko
2026-08-13 15:45     ` Jan Beulich
2026-08-04 15:48 ` [PATCH v7 12/20] xen/riscv: introduce minimal virtual APLIC (vAPLIC) infrastructure Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 13/20] xen/riscv: introduce (de)initialization helpers for vINTC Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 14/20] xen/riscv: generate IMSIC DT node for guest domains Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 15/20] xen/riscv: create APLIC " Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 16/20] xen/riscv: implement IRQ routing for device passthrough Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 17/20] xen/riscv: implement init_intc_phandle() Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 18/20] xen/riscv: initialize RCU, scheduler, and system domains in start_xen() Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 19/20] xen/riscv: provide init_vuart() Oleksii Kurochko
2026-08-04 15:48 ` [PATCH v7 20/20] xen/riscv: add initial dom0less infrastructure support Oleksii Kurochko

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9abc0091-43e5-475e-ae61-697f480dda5e@gmail.com \
    --to=oleksii.kurochko@gmail.com \
    --cc=Romain.Caritey@microchip.com \
    --cc=alistair.francis@wdc.com \
    --cc=andrew.cooper3@citrix.com \
    --cc=anthony.perard@vates.tech \
    --cc=baptiste.le-duc@vates.tech \
    --cc=connojdavis@gmail.com \
    --cc=jbeulich@suse.com \
    --cc=julien@xen.org \
    --cc=michal.orzel@amd.com \
    --cc=roger@xenproject.org \
    --cc=sstabellini@kernel.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.