All of lore.kernel.org
 help / color / mirror / Atom feed
From: Vasant Hegde <vasant.hegde@amd.com>
To: Jason Gunthorpe <jgg@ziepe.ca>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
	suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
	jsnitsel@redhat.com
Subject: Re: [PATCH v2 05/11] iommu/amd: Add support to enable/disable PASID feature
Date: Fri, 15 Sep 2023 14:27:51 +0530	[thread overview]
Message-ID: <9b134256-b093-e16b-3e46-2e9bc42de53d@amd.com> (raw)
In-Reply-To: <ZQCYhVD+rudRtnFl@ziepe.ca>

Jason,


On 9/12/2023 10:27 PM, Jason Gunthorpe wrote:
> On Mon, Sep 11, 2023 at 12:10:40PM +0000, Vasant Hegde wrote:
>> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>>
>> It seems iommu_dev_enable_feature(SVA) will be deprecated soon. Hence in
>> this path we just return success.
>>
>> Instead we add necessary check during pasid bind to device. IN this path
>> it checks whether device GCR3 table is setup or not. If not it will try
>> to setup the GCR3.
> 
> Yes, though be mindful that switching from IDENTITY v1 to IDENTITY v2
> on the RID (eg switching the DTE to/from GCR3 mode) should be atomic.

Right. Its atomic. It should work fine. I have to be careful when I add support
for PASID table expansion. But its doable.

> 
>> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
>> index 94eec3dac8f6..5a9749cfe14e 100644
>> --- a/drivers/iommu/amd/iommu.c
>> +++ b/drivers/iommu/amd/iommu.c
>> @@ -2162,6 +2162,50 @@ static void protection_domain_free(struct protection_domain *domain)
>>  	kfree(domain);
>>  }
>>  
>> +/*******************************
>> + * PASID setup related helper functions
>> + */
>> +static inline bool pdom_is_pt_mode(struct protection_domain *pdom)
>> +{
>> +	return (pdom->domain.type == IOMMU_DOMAIN_IDENTITY);
>> +}
>> +
>> +static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom)
>> +{
>> +	return (pdom->iop.pgd != NULL);
>> +}
>> +
>> +int amd_iommu_gcr3_init(struct iommu_dev_data *dev_data, int pasids)
>> +{
>> +	struct protection_domain *pdom = dev_data->domain;
>> +	int ret = 0;
>> +
>> +	lockdep_assert_held(&dev_data->lock);
>> +
>> +	/*
>> +	 * We cannot support PASID w/ existing v1 page table in the same domain
>> +	 * since it will be nested. However, existing domain w/ v2 page table
>> +	 * can be used for PASID.
>> +	 */
>> +	if (pdom->pd_mode == PD_MODE_V1)
>> +		return -EOPNOTSUPP;
>> +
>> +	/* Allocate GCR3 table */
>> +	if (pdom_is_pt_mode(dev_data->domain))
> 
> It seems obfuscating to put this test for IOMMU_DOMAIN_IDENTITY in a
> function..

It needs to know how domain is configured. Hence I have this check.

> 
>> +		ret = setup_gcr3_table(dev_data, pasids);
> 
> This is the DTE change that should be atomic

It gets called with dev_data lock. And it doesn't break ongoing translations. So
it should be fine.

-Vasant

  reply	other threads:[~2023-09-15  8:58 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-11 12:10 [PATCH v2 00/11] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 01/11] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_sva_supported() Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 02/11] iommu/amd: Do not override PASID entry in GCR3 table Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 03/11] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 04/11] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2023-09-12 16:47   ` Jason Gunthorpe
2023-09-15  8:50     ` Vasant Hegde
2023-09-18 12:53       ` Jason Gunthorpe
2023-10-13 15:52         ` Vasant Hegde
2023-10-13 15:58           ` Jason Gunthorpe
2023-09-11 12:10 ` [PATCH v2 05/11] iommu/amd: Add support to enable/disable PASID feature Vasant Hegde
2023-09-12 16:57   ` Jason Gunthorpe
2023-09-15  8:57     ` Vasant Hegde [this message]
2023-09-11 12:10 ` [PATCH v2 06/11] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 07/11] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2023-09-12 16:59   ` Jason Gunthorpe
2023-09-15 13:48     ` Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 08/11] iommu/amd: Add support for page response Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 09/11] iommu/amd: Add support for add/remove device for IOPF Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 10/11] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2023-09-12 18:46   ` Jason Gunthorpe
2023-09-13  4:19     ` Baolu Lu
2023-09-15  8:15     ` Vasant Hegde
2023-09-11 12:10 ` [PATCH v2 11/11] iommu/amd: Introduce logic to enable/disable IOPF Vasant Hegde
2023-09-12 16:32   ` Jason Gunthorpe
2023-09-15  8:26     ` Vasant Hegde
2023-09-18 12:45       ` Jason Gunthorpe
2023-10-10 14:53         ` Vasant Hegde
2023-10-10 15:04           ` Jason Gunthorpe
2023-09-12 18:48 ` [PATCH v2 00/11] iommu/amd: SVA Support (Part 4) - SVA and IOPF Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9b134256-b093-e16b-3e46-2e9bc42de53d@amd.com \
    --to=vasant.hegde@amd.com \
    --cc=iommu@lists.linux.dev \
    --cc=jgg@ziepe.ca \
    --cc=joro@8bytes.org \
    --cc=jsnitsel@redhat.com \
    --cc=suravee.suthikulpanit@amd.com \
    --cc=wei.huang2@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.