diff for duplicates of <9b343fd1-15df-409a-390f-e30fa6bbbfe7@gmail.com> diff --git a/a/1.txt b/N1/1.txt index fe08b39..ad7b52d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ 10.03.2020 18:19, Thierry Reding пишет: -> From: Joseph Lo <josephl@nvidia.com> +> From: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > Introduce the low jitter path of PLLP and PLLMB which can be used as EMC > clock source. > -> Signed-off-by: Joseph Lo <josephl@nvidia.com> -> Signed-off-by: Thierry Reding <treding@nvidia.com> +> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++ > include/dt-bindings/clock/tegra210-car.h | 4 ++-- diff --git a/a/content_digest b/N1/content_digest index 3e44c32..454da37 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,29 +1,30 @@ "ref\020200310152003.2945170-1-thierry.reding@gmail.com\0" "ref\020200310152003.2945170-2-thierry.reding@gmail.com\0" - "From\0Dmitry Osipenko <digetx@gmail.com>\0" + "ref\020200310152003.2945170-2-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "Subject\0Re: [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210\0" "Date\0Tue, 10 Mar 2020 19:19:59 +0300\0" - "To\0Thierry Reding <thierry.reding@gmail.com>\0" - "Cc\0Jon Hunter <jonathanh@nvidia.com>" - Rob Herring <robh+dt@kernel.org> - Mark Rutland <mark.rutland@arm.com> - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@kernel.org> - Joseph Lo <josephl@nvidia.com> - devicetree@vger.kernel.org - linux-tegra@vger.kernel.org - linux-clk@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Stephen Boyd <sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "10.03.2020 18:19, Thierry Reding \320\277\320\270\321\210\320\265\321\202:\n" - "> From: Joseph Lo <josephl@nvidia.com>\n" + "> From: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> \n" "> Introduce the low jitter path of PLLP and PLLMB which can be used as EMC\n" "> clock source.\n" "> \n" - "> Signed-off-by: Joseph Lo <josephl@nvidia.com>\n" - "> Signed-off-by: Thierry Reding <treding@nvidia.com>\n" + "> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> ---\n" "> drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++\n" "> include/dt-bindings/clock/tegra210-car.h | 4 ++--\n" @@ -51,4 +52,4 @@ "Isn't it possible to auto-enable the low-jitter bit when necessary\n" during of the rate-change based on a given clock-rate? -6bcef140334c9c1ef31aa317d6a935c61ecafe1d92ea41190a9965d4e4fae3d2 +0d29ad6fad7f9d0591f13f77fbd00b7300d9e94e4d5db8c31d871855855d50ff
diff --git a/a/1.txt b/N2/1.txt index fe08b39..a15cb8b 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -32,3 +32,8 @@ Isn't it possible to auto-enable the low-jitter bit when necessary during of the rate-change based on a given clock-rate? + +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N2/content_digest index 3e44c32..7567466 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,13 +4,13 @@ "Subject\0Re: [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210\0" "Date\0Tue, 10 Mar 2020 19:19:59 +0300\0" "To\0Thierry Reding <thierry.reding@gmail.com>\0" - "Cc\0Jon Hunter <jonathanh@nvidia.com>" - Rob Herring <robh+dt@kernel.org> - Mark Rutland <mark.rutland@arm.com> - Michael Turquette <mturquette@baylibre.com> + "Cc\0Mark Rutland <mark.rutland@arm.com>" + devicetree@vger.kernel.org Stephen Boyd <sboyd@kernel.org> + Michael Turquette <mturquette@baylibre.com> + Jon Hunter <jonathanh@nvidia.com> + Rob Herring <robh+dt@kernel.org> Joseph Lo <josephl@nvidia.com> - devicetree@vger.kernel.org linux-tegra@vger.kernel.org linux-clk@vger.kernel.org " linux-arm-kernel@lists.infradead.org\0" @@ -49,6 +49,11 @@ "> +\tclks[TEGRA210_CLK_PLL_P_UD] = clk;\n" "\n" "Isn't it possible to auto-enable the low-jitter bit when necessary\n" - during of the rate-change based on a given clock-rate? + "during of the rate-change based on a given clock-rate?\n" + "\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -6bcef140334c9c1ef31aa317d6a935c61ecafe1d92ea41190a9965d4e4fae3d2 +3c6c70a2a2621ce9b745c9bc159fe131c5f3ef6da8e19aa1f921ca7e83be9d34
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