From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Yi Lai <yi1.lai@intel.com>
Subject: Re: [PATCH 1/3] perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag
Date: Thu, 17 Jul 2025 17:09:05 +0800 [thread overview]
Message-ID: <9b4651bf-20e4-406f-ba41-9f67515e5bea@linux.intel.com> (raw)
In-Reply-To: <20250717090302.11316-1-dapeng1.mi@linux.intel.com>
Run basic perf counting, PMI based sampling and PEBS based sampling on
Intel Sapphire Rapids, Granite Rapids and Sierra Forest platforms, no issue
is found.
On 7/17/2025 5:03 PM, Dapeng Mi wrote:
> IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to
> indicate whether timed PEBS is supported. Timed PEBS adds a new "retired
> latency" field in basic info group to show the timing info. Please find
> detailed information about timed PEBS in section 8.4.1 "Timed Processor
> Event Based Sampling" of "Intel Architecture Instruction Set Extensions
> and Future Features".
>
> This patch adds PERF_CAP_PEBS_TIMING_INFO flag and KVM module leverages
> this flag to expose timed PEBS feature to guest.
>
> Moreover, opportunistically refine the indents and make the macros
> share consistent indents.
>
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Tested-by: Yi Lai <yi1.lai@intel.com>
> ---
> arch/x86/include/asm/msr-index.h | 14 ++++++++------
> tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------
> 2 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index b7dded3c8113..48b7ed28718c 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -315,12 +315,14 @@
> #define PERF_CAP_PT_IDX 16
>
> #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
> -#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
> -#define PERF_CAP_ARCH_REG BIT_ULL(7)
> -#define PERF_CAP_PEBS_FORMAT 0xf00
> -#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
> -#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> - PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
> +#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
> +#define PERF_CAP_ARCH_REG BIT_ULL(7)
> +#define PERF_CAP_PEBS_FORMAT 0xf00
> +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
> +#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17)
> +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
> + PERF_CAP_PEBS_TIMING_INFO)
>
> #define MSR_IA32_RTIT_CTL 0x00000570
> #define RTIT_CTL_TRACEEN BIT(0)
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index b7dded3c8113..48b7ed28718c 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -315,12 +315,14 @@
> #define PERF_CAP_PT_IDX 16
>
> #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
> -#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
> -#define PERF_CAP_ARCH_REG BIT_ULL(7)
> -#define PERF_CAP_PEBS_FORMAT 0xf00
> -#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
> -#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> - PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
> +#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
> +#define PERF_CAP_ARCH_REG BIT_ULL(7)
> +#define PERF_CAP_PEBS_FORMAT 0xf00
> +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
> +#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17)
> +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
> + PERF_CAP_PEBS_TIMING_INFO)
>
> #define MSR_IA32_RTIT_CTL 0x00000570
> #define RTIT_CTL_TRACEEN BIT(0)
>
> base-commit: 829f5a6308ce11c3edaa31498a825f8c41b9e9aa
prev parent reply other threads:[~2025-07-17 9:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-17 9:03 [PATCH 1/3] perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag Dapeng Mi
2025-07-17 9:03 ` [PATCH 2/3] perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48) Dapeng Mi
2025-07-17 9:03 ` [PATCH 3/3] perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into INTEL_FIXED_BITS_MASK Dapeng Mi
2025-07-17 9:09 ` Mi, Dapeng [this message]
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