From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id 0921CC5CFC1 for ; Fri, 15 Jun 2018 10:17:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE039208C3 for ; Fri, 15 Jun 2018 10:17:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE039208C3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936283AbeFOKQy (ORCPT ); Fri, 15 Jun 2018 06:16:54 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40750 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934900AbeFOKQu (ORCPT ); Fri, 15 Jun 2018 06:16:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19F381529; Fri, 15 Jun 2018 03:16:50 -0700 (PDT) Received: from [10.1.206.73] (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7183C3F557; Fri, 15 Jun 2018 03:16:47 -0700 (PDT) Subject: Re: [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking To: Julien Thierry , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com References: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> <1527241772-48007-3-git-send-email-julien.thierry@arm.com> <54ff6127-928d-99a3-a6e9-59799628ca87@arm.com> <3f0afa54-8e98-798e-68dc-bbbc74bd9e19@arm.com> From: Suzuki K Poulose Message-ID: <9b87c045-e925-a412-f750-ef2c94e50de5@arm.com> Date: Fri, 15 Jun 2018 11:16:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/06/18 14:46, Julien Thierry wrote: > > > On 25/05/18 11:48, Julien Thierry wrote: >> >> >> On 25/05/18 11:41, Suzuki K Poulose wrote: >>> On 25/05/18 11:39, Julien Thierry wrote: >>>> >>>> >>>> On 25/05/18 11:36, Suzuki K Poulose wrote: >>>>> On 25/05/18 11:17, Julien Thierry wrote: >>>>>> >>>>>> >>>>>> On 25/05/18 11:04, Suzuki K Poulose wrote: >>>>>>> On 25/05/18 10:49, Julien Thierry wrote: >>>>>>>> Add a cpufeature indicating whether a cpu supports masking interrupts >>>>>>>> by priority. >>>>>>> >>>>>>> How is this different from the SYSREG_GIC_CPUIF cap ? Is it just >>>>>>> the description ? >>>>>> >>>>>> More or less. >>>>>> >>>>>> It is just to have an easier condition in the rest of the series. Basically the PRIO masking feature is enabled if we have a GICv3 CPUIF working *and* the option was selected at build time. Before this meant that I was checking for the GIC_CPUIF cap inside #ifdefs (and putting alternatives depending on that inside #ifdefs as well). >>>>>> >>>>>> Having this as a separate feature feels easier to manage in the code. It also makes it clearer at boot time that the kernel will be using irq priorities (although I admit it was not the initial intention): >>>>>> >>>>>> [    0.000000] CPU features: detected: IRQ priority masking >>>>>> >>>>>> >>>>>> But yes that new feature will be detected only if SYSREG_GIC_CPUIF gets detected as well. >>>>> >>>>> Well, you could always wrap the check like : >>>>> >>>>> static inline bool system_has_irq_priority_masking(void) >>>>> { >>>>>      return (IS_ENABLED(CONFIG_YOUR_CONFIG) && cpus_have_const_cap(HWCAP_SYSREG_GIC_CPUIF)); >>>>> } >>>>> >>>>> and use it everywhere. >>>>> >>>> >>>> Yes, but I can't use that in the asm parts that use alternatives and would need to surround them in #ifdef... :\ >>> >>> I thought there is _ALTERNATIVE_CFG() to base the alternative depend on a CONFIG_xxx ? >>> Doesn't that solve the problem ? >> >> Right, I didn't see that one. It should work yes. >> >> I'll try that when working on the next version. > > I've been trying to use this now, but I can't figure out how. > > The _ALTERNATIVE_CFG does not seem to work in assembly code (despite having its own definition for __ASSEMBLY__), and the alternative_insn does not seem to be suited for instructions that take operands (or more than one operand) > > If I am mistaken, can you provide an example of how to use this in assembly with instructions having more than 1 operand? I am sorry, but I think the ALTERNATIVE_CFG is not the right one, as it omits the entire block, if the CONFIG is not enabled. So you are left with only three choices : 1) Use alternative call back 2) Stick to two separate caps. 3) Use #ifdef Cheers Suzuki From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suzuki.Poulose@arm.com (Suzuki K Poulose) Date: Fri, 15 Jun 2018 11:16:45 +0100 Subject: [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking In-Reply-To: References: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> <1527241772-48007-3-git-send-email-julien.thierry@arm.com> <54ff6127-928d-99a3-a6e9-59799628ca87@arm.com> <3f0afa54-8e98-798e-68dc-bbbc74bd9e19@arm.com> Message-ID: <9b87c045-e925-a412-f750-ef2c94e50de5@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/06/18 14:46, Julien Thierry wrote: > > > On 25/05/18 11:48, Julien Thierry wrote: >> >> >> On 25/05/18 11:41, Suzuki K Poulose wrote: >>> On 25/05/18 11:39, Julien Thierry wrote: >>>> >>>> >>>> On 25/05/18 11:36, Suzuki K Poulose wrote: >>>>> On 25/05/18 11:17, Julien Thierry wrote: >>>>>> >>>>>> >>>>>> On 25/05/18 11:04, Suzuki K Poulose wrote: >>>>>>> On 25/05/18 10:49, Julien Thierry wrote: >>>>>>>> Add a cpufeature indicating whether a cpu supports masking interrupts >>>>>>>> by priority. >>>>>>> >>>>>>> How is this different from the SYSREG_GIC_CPUIF cap ? Is it just >>>>>>> the description ? >>>>>> >>>>>> More or less. >>>>>> >>>>>> It is just to have an easier condition in the rest of the series. Basically the PRIO masking feature is enabled if we have a GICv3 CPUIF working *and* the option was selected at build time. Before this meant that I was checking for the GIC_CPUIF cap inside #ifdefs (and putting alternatives depending on that inside #ifdefs as well). >>>>>> >>>>>> Having this as a separate feature feels easier to manage in the code. It also makes it clearer at boot time that the kernel will be using irq priorities (although I admit it was not the initial intention): >>>>>> >>>>>> [??? 0.000000] CPU features: detected: IRQ priority masking >>>>>> >>>>>> >>>>>> But yes that new feature will be detected only if SYSREG_GIC_CPUIF gets detected as well. >>>>> >>>>> Well, you could always wrap the check like : >>>>> >>>>> static inline bool system_has_irq_priority_masking(void) >>>>> { >>>>> ?????return (IS_ENABLED(CONFIG_YOUR_CONFIG) && cpus_have_const_cap(HWCAP_SYSREG_GIC_CPUIF)); >>>>> } >>>>> >>>>> and use it everywhere. >>>>> >>>> >>>> Yes, but I can't use that in the asm parts that use alternatives and would need to surround them in #ifdef... :\ >>> >>> I thought there is _ALTERNATIVE_CFG() to base the alternative depend on a CONFIG_xxx ? >>> Doesn't that solve the problem ? >> >> Right, I didn't see that one. It should work yes. >> >> I'll try that when working on the next version. > > I've been trying to use this now, but I can't figure out how. > > The _ALTERNATIVE_CFG does not seem to work in assembly code (despite having its own definition for __ASSEMBLY__), and the alternative_insn does not seem to be suited for instructions that take operands (or more than one operand) > > If I am mistaken, can you provide an example of how to use this in assembly with instructions having more than 1 operand? I am sorry, but I think the ALTERNATIVE_CFG is not the right one, as it omits the entire block, if the CONFIG is not enabled. So you are left with only three choices : 1) Use alternative call back 2) Stick to two separate caps. 3) Use #ifdef Cheers Suzuki