From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 153CFCDB46F for ; Tue, 23 Jun 2026 14:43:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5BB810EB8B; Tue, 23 Jun 2026 14:43:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SeirOUdE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD44910EB8B; Tue, 23 Jun 2026 14:43:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782225815; x=1813761815; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version:content-id; bh=zkDWHGwd+QQlouaXI7rroYqVARGLA4uHTWnI61FueNI=; b=SeirOUdEolg3yBFRVeeyoJ4PWgqvlH7ul16Y65/+J7/f4G2gX34FHrmP NDFzcJPewbIVwl0Pou715F17/hycgs6xDq8Gs/yfqzdhsBiD4xH6XT1g0 kLut2TnPeJWKBV8Si6drp9vqb0zmbRVS4mSiXek+3yl7trPqN8UhDmajx zJZpIyrJ9U0vvSeBawNH17UOApAqzhQkWodYIkIv6eDUB10OZqRFd79Kf hutiW0FhVvOjWHPtyk75CadeXfTtAFmq07AprLvQ7n4y0y82XNEXXp6Fo WuGlWZETqK4c1L15HpQyalKJXvk07I5mXMgts72lK6BlygHSuHIpRzXOr g==; X-CSE-ConnectionGUID: 8P3/z7LxShmGZ/GrVkQISA== X-CSE-MsgGUID: lzaC6KyQRD+6uxcjC3ei9g== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="93558865" X-IronPort-AV: E=Sophos;i="6.24,220,1774335600"; d="scan'208";a="93558865" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 07:43:34 -0700 X-CSE-ConnectionGUID: jL4L2cGNR8y83cAQ0Y1Jww== X-CSE-MsgGUID: Rcre7mNqQLSk3lYa6ZV2tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,220,1774335600"; d="scan'208";a="245400037" Received: from dev-417.igk.intel.com ([10.91.214.181]) by fmviesa010.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 07:43:33 -0700 Date: Tue, 23 Jun 2026 16:43:31 +0200 (CEST) From: =?ISO-8859-2?Q?Micha=B3_Grzelak?= To: Ville Syrjala cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: Re: [PATCH 1/6] drm/i915/gmbus: Rename GPIO pins In-Reply-To: <20260623125111.6632-2-ville.syrjala@linux.intel.com> Message-ID: <9be069dc-e1f0-bf15-7506-b40fa867c71e@intel.com> References: <20260623125111.6632-1-ville.syrjala@linux.intel.com> <20260623125111.6632-2-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="8323329-486462598-1782223389=:605841" Content-ID: <9e05adb0-ea38-0942-dd79-6dbc4a12f577@intel.com> X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-486462598-1782223389=:605841 Content-Type: text/plain; CHARSET=ISO-8859-2; format=flowed Content-Transfer-Encoding: 8BIT Content-ID: <60ef332b-911e-3496-3e2d-396a25aae6c3@intel.com> On Tue, 23 Jun 2026, Ville Syrjala wrote: > From: Ville Syrjälä > > Replace the alphabetical GPIOA,GPIOB,... with numeric > GPIO_0,GPIO_1,... This makes the naming scheme agree with > BSpec. No idea why the alphabetical naming was originally > chosen as BSpec never used that convention for the GPIO pins. > > Signed-off-by: Ville Syrjälä How do you see in general adding BSpec no. into trailers, here eg. 49306, 49311 or 68971? Does it make sense, or not really? Reviewed-by: Micha³ Grzelak BR, Micha³ > --- > drivers/gpu/drm/i915/display/intel_gmbus.c | 124 ++++++++++----------- > 1 file changed, 62 insertions(+), 62 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c > index 049157c41fe2..9990e6391b03 100644 > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c > @@ -54,21 +54,21 @@ struct intel_gmbus { > }; > > enum gmbus_gpio { > - GPIOA, > - GPIOB, > - GPIOC, > - GPIOD, > - GPIOE, > - GPIOF, > - GPIOG, > - GPIOH, > - __GPIOI_UNUSED, > - GPIOJ, > - GPIOK, > - GPIOL, > - GPIOM, > - GPION, > - GPIOO, > + GPIO_0, > + GPIO_1, > + GPIO_2, > + GPIO_3, > + GPIO_4, > + GPIO_5, > + GPIO_6, > + GPIO_7, > + GPIO_8, > + GPIO_9, > + GPIO_10, > + GPIO_11, > + GPIO_12, > + GPIO_13, > + GPIO_14, > }; > > struct gmbus_pin { > @@ -78,77 +78,77 @@ struct gmbus_pin { > > /* Map gmbus pin pairs to names and registers. */ > static const struct gmbus_pin gmbus_pins[] = { > - [GMBUS_PIN_SSC] = { "ssc", GPIOB }, > - [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, > - [GMBUS_PIN_PANEL] = { "panel", GPIOC }, > - [GMBUS_PIN_DPC] = { "dpc", GPIOD }, > - [GMBUS_PIN_DPB] = { "dpb", GPIOE }, > - [GMBUS_PIN_DPD] = { "dpd", GPIOF }, > + [GMBUS_PIN_SSC] = { "ssc", GPIO_1 }, > + [GMBUS_PIN_VGADDC] = { "vga", GPIO_0 }, > + [GMBUS_PIN_PANEL] = { "panel", GPIO_2 }, > + [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, > + [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, > }; > > static const struct gmbus_pin gmbus_pins_bdw[] = { > - [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, > - [GMBUS_PIN_DPC] = { "dpc", GPIOD }, > - [GMBUS_PIN_DPB] = { "dpb", GPIOE }, > - [GMBUS_PIN_DPD] = { "dpd", GPIOF }, > + [GMBUS_PIN_VGADDC] = { "vga", GPIO_0 }, > + [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, > + [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, > }; > > static const struct gmbus_pin gmbus_pins_skl[] = { > - [GMBUS_PIN_DPC] = { "dpc", GPIOD }, > - [GMBUS_PIN_DPB] = { "dpb", GPIOE }, > - [GMBUS_PIN_DPD] = { "dpd", GPIOF }, > + [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, > + [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, > }; > > static const struct gmbus_pin gmbus_pins_bxt[] = { > - [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, > - [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, > - [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, > + [GMBUS_PIN_1_BXT] = { "dpb", GPIO_1 }, > + [GMBUS_PIN_2_BXT] = { "dpc", GPIO_2 }, > + [GMBUS_PIN_3_BXT] = { "misc", GPIO_3 }, > }; > > static const struct gmbus_pin gmbus_pins_cnp[] = { > - [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, > - [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, > - [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, > - [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, > + [GMBUS_PIN_1_BXT] = { "dpb", GPIO_1 }, > + [GMBUS_PIN_2_BXT] = { "dpc", GPIO_2 }, > + [GMBUS_PIN_3_BXT] = { "misc", GPIO_3 }, > + [GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 }, > }; > > static const struct gmbus_pin gmbus_pins_icp[] = { > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, > - [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, > - [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, > - [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, > + [GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 }, > + [GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 }, > + [GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIO_9 }, > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIO_10 }, > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIO_11 }, > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIO_12 }, > + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPIO_13 }, > + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIO_14 }, > }; > > static const struct gmbus_pin gmbus_pins_dg1[] = { > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, > - [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, > - [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, > + [GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 }, > + [GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 }, > + [GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 }, > }; > > static const struct gmbus_pin gmbus_pins_dg2[] = { > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, > - [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, > - [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, > + [GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 }, > + [GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 }, > + [GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 }, > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIO_9 }, > }; > > static const struct gmbus_pin gmbus_pins_mtp[] = { > - [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, > - [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, > - [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, > - [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, > - [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, > - [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, > - [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, > - [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, > - [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, > + [GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 }, > + [GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 }, > + [GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 }, > + [GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 }, > + [GMBUS_PIN_5_MTP] = { "dpe", GPIO_5 }, > + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIO_9 }, > + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIO_10 }, > + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIO_11 }, > + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIO_12 }, > }; > > static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, > -- > 2.53.0 > > --8323329-486462598-1782223389=:605841--