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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB7183.namprd11.prod.outlook.com (2603:10b6:8:111::10) by PH0PR11MB4997.namprd11.prod.outlook.com (2603:10b6:510:31::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.17; Thu, 21 May 2026 12:35:56 +0000 Received: from DM4PR11MB7183.namprd11.prod.outlook.com ([fe80::d9c7:d2fb:680d:1ee1]) by DM4PR11MB7183.namprd11.prod.outlook.com ([fe80::d9c7:d2fb:680d:1ee1%5]) with mapi id 15.21.0025.022; Thu, 21 May 2026 12:35:56 +0000 Message-ID: <9c4928ff-6520-4dbd-92ee-2fc49c2630ca@intel.com> Date: Thu, 21 May 2026 18:05:47 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG To: "Manna, Animesh" , "intel-gfx@lists.freedesktop.org" , "intel-xe@lists.freedesktop.org" CC: "Shankar, Uma" , "ville.syrjala@linux.intel.com" , "Nikula, Jani" References: <20260513163857.1541888-1-animesh.manna@intel.com> <20260513163857.1541888-2-animesh.manna@intel.com> <074e4d37-9bf0-45da-9541-8b27164e743c@intel.com> Content-Language: en-US From: Dibin Moolakadan Subrahmanian In-Reply-To: Content-Type: text/plain; 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intel- >> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org >> Cc: Shankar, Uma ; ville.syrjala@linux.intel.com; >> Nikula, Jani >> Subject: Re: [PATCH v6 01/16] drm/i915/cmtg: Add intel_cmtg_is_allowed() >> for CMTG >> >> >> On 13-05-2026 22:08, Animesh Manna wrote: >>> CMTG will be enabled only with DC3co, so add a separate function >>> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG. >>> DC3co will be enabled in a separate patch. >>> >>> v2: >>> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin] >>> >>> v3: >>> - Do not access power domain members directly. [Jani] >>> >>> Signed-off-by: Animesh Manna >>> --- >>> drivers/gpu/drm/i915/display/intel_cmtg.c | 15 ++++++++++++++- >>> drivers/gpu/drm/i915/display/intel_cmtg.h | 4 ++++ >>> 2 files changed, 18 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c >>> b/drivers/gpu/drm/i915/display/intel_cmtg.c >>> index e1fdc6fe9762..dc039bea452c 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c >>> @@ -4,7 +4,6 @@ >>> */ >>> >>> #include >>> -#include >>> >>> #include >>> #include >>> @@ -16,6 +15,7 @@ >>> #include "intel_display_device.h" >>> #include "intel_display_power.h" >>> #include "intel_display_regs.h" >>> +#include "intel_display_types.h" >>> >>> /** >>> * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +185,16 >> @@ >>> void intel_cmtg_sanitize(struct intel_display *display) >>> >>> intel_cmtg_disable(display, &cmtg_config); >>> } >>> + >>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) >>> +{ >>> + struct intel_display *display = to_intel_display(crtc_state); >>> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >>> + >>> + if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == >> TRANSCODER_B) && >>> + DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, >> INTEL_OUTPUT_EDP) && >>> + intel_display_power_get_current_dc_state(display) == >>> +DC_STATE_EN_DC3CO) >> I would enable CMTG before setting the DC3CO state, since CMTG running is >> a must condition for DC3CO. >> Doing it the current way creates a cyclic dependency. > Copy -pasting from bspec: > CMTG must be enabled with dynamic DC states.​​​ > > Dynamic DC state refers to Dc3co/Dc6v. > So added a check for dc-state which will be used inside cmtg functions. Do not want to allow touching CMTG register if target_dc_state is not DC3co. > > Again copy-pasting from bspec: > CMTG state needs to be saved and restored during power state transitions. > > Which means CMTG will lose its value with DC5/DC6. So want to be little cautious while handling CMTG. I can see DC6 restore is already handled in patch 15. target_dc_state is a software state doesn't guarantee any actual DC state register write. I think its better to leave the target dc state decision to DC3CO implementation rather than using it as flag variable for CMTG enable check. > > We should finalize what will be the target_dc_state based use case like PSR2/LOBF/PR-ALPM and single EDP configuration. > This is the only flag and based on that CMTG and DC3co will be enabled. So, no cyclic dependency. Good to know if I am missing anything. > > Regards, > Animesh > >>> + return true; >>> + >>> + return false; >>> +} >>> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h >>> b/drivers/gpu/drm/i915/display/intel_cmtg.h >>> index ba62199adaa2..ed540581738f 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h >>> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h >>> @@ -6,8 +6,12 @@ >>> #ifndef __INTEL_CMTG_H__ >>> #define __INTEL_CMTG_H__ >>> >>> +#include >>> + >>> struct intel_display; >>> +struct intel_crtc_state; >>> >>> void intel_cmtg_sanitize(struct intel_display *display); >>> +bool intel_cmtg_is_allowed(const struct intel_crtc_state >>> +*crtc_state); >>> >>> #endif /* __INTEL_CMTG_H__ */