Re: [PATCH v4 4/5] vpci: add SR-IOV support for PVH Dom0

[Jason Andryuk <jason.andryuk@amd.com>]

On 2026-10-19 17:47, Jason Andryuk wrote:
> On 2026-10-15 10:08, Mykyta Poturai wrote:
>> From: Stewart Hildebrand <stewart.hildebrand@amd.com>

>> +        struct vpci_bar *bar = &bars[i];
>> +
>> +        /*
>> +         * The upper half of a 64-bit BAR holds no address or size of 
>> its own;
>> +         * the handlers reach the lower half through its type alone.
>> +         */
>> +        if ( pf_bar->type == VPCI_BAR_MEM64_HI )
>> +        {
>> +            bar->type = VPCI_BAR_MEM64_HI;
>> +            continue;
>> +        }
>> +
>> +        if ( pf_bar->type != VPCI_BAR_MEM32 &&
>> +             pf_bar->type != VPCI_BAR_MEM64_LO )
>> +            continue;
>> +
>> +        bar->addr         = pf_bar->addr + vf_idx * pf_bar->size;
> AIUI, the PF has the SR-IOV BARs, which are sized like normal.  But I 
> thought the pf_bar->size needs to be reduced by some factor to get the 
> per-VF size.  I can't find where that is done.  Or am I wrong about this?
Ok, I looked around and I think I was wrong.  The SR-IOV bar returns the 
single VF size, and it is up to the OS to multiply by the number of VFs.

Thanks,
Jason