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X-CSE-ConnectionGUID: uCnmjb52SLy+qgvKF3ka7A== X-CSE-MsgGUID: /zCnWu80RG6RCYRZ10czgA== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="91269236" X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="91269236" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 21:34:06 -0800 X-CSE-ConnectionGUID: tCSWuHajQISJOM7eQNBNqA== X-CSE-MsgGUID: YcADNc1KT9GnB0ZdlfW55w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="215630782" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.241.147]) ([10.124.241.147]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 21:34:03 -0800 Message-ID: <9d74db3d-49d0-493f-9c68-da5d97f9c45e@linux.intel.com> Date: Fri, 6 Mar 2026 13:34:01 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 12/13] target/i386: Clean up Intel Debug Store feature dependencies To: Zide Chen , qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang References: <20260304180713.360471-1-zide.chen@intel.com> <20260304180713.360471-13-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260304180713.360471-13-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reviewed-by: Dapeng Mi On 3/5/2026 2:07 AM, Zide Chen wrote: > - 64-bit DS Area (CPUID.01H:ECX[2]) depends on DS (CPUID.01H:EDX[21]). > - When PMU is disabled, Debug Store must not be exposed to the guest, > which implicitly disables legacy DS-based PEBS. > > Signed-off-by: Zide Chen > --- > V3: > - Update title to be more accurate. > - Make DTES64 depend on DS. > - Mark MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL in previous patch. > - Clean up the commit message. > > V2: New patch. > --- > target/i386/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 2e1dea65d708..3ff9f76cf7da 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1899,6 +1899,10 @@ static FeatureDep feature_dependencies[] = { > .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, > .to = { FEAT_PERF_CAPABILITIES, ~0ull }, > }, > + { > + .from = { FEAT_1_EDX, CPUID_DTS}, > + .to = { FEAT_1_ECX, CPUID_EXT_DTES64}, > + }, > { > .from = { FEAT_1_ECX, CPUID_EXT_VMX }, > .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, > @@ -9471,6 +9475,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) > env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; > } > > + env->features[FEAT_1_EDX] &= ~CPUID_DTS; > env->features[FEAT_7_0_EDX] &= ~CPUID_7_0_EDX_ARCH_LBR; > } >