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([2804:431:c7c7:52e2:fb25:323c:5709:7237]) by smtp.gmail.com with ESMTPSA id c18-20020a67f8d2000000b003861d2f31efsm4602499vsp.3.2022.08.03.02.09.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Aug 2022 02:09:35 -0700 (PDT) Message-ID: <9e113398-e0cd-7902-a910-654eaedde56d@gmail.com> Date: Wed, 3 Aug 2022 06:09:33 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 06/19] ppc/ppc405: QOM'ify CPU Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, BALATON Zoltan References: <20220801131039.1693913-1-clg@kaod.org> <20220801131039.1693913-7-clg@kaod.org> From: Daniel Henrique Barboza In-Reply-To: <20220801131039.1693913-7-clg@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=danielhb413@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/1/22 10:10, Cédric Le Goater wrote: > Drop the use of ppc4xx_init() and duplicate a bit of code related to > clocks in the SoC realize routine. We will clean that up in the > following patches. > > ppc_dcr_init simply allocates default DCR handlers for the CPU. Maybe > this could be done in model initializer of the CPU families needing it. > > Signed-off-by: Cédric Le Goater > --- Reviewed-by: Daniel Henrique Barboza > hw/ppc/ppc405.h | 2 +- > hw/ppc/ppc405_boards.c | 2 +- > hw/ppc/ppc405_uc.c | 34 ++++++++++++++++++++++++---------- > 3 files changed, 26 insertions(+), 12 deletions(-) > > diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h > index 5e4e96d86ceb..4e99ab48be36 100644 > --- a/hw/ppc/ppc405.h > +++ b/hw/ppc/ppc405.h > @@ -80,7 +80,7 @@ struct Ppc405SoCState { > hwaddr ram_size; > > uint32_t sysclk; > - PowerPCCPU *cpu; > + PowerPCCPU cpu; > DeviceState *uic; > }; > > diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c > index 363cb0770506..82b51cc457fa 100644 > --- a/hw/ppc/ppc405_boards.c > +++ b/hw/ppc/ppc405_boards.c > @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine) > > /* Load ELF kernel and rootfs.cpio */ > } else if (kernel_filename && !machine->firmware) { > - boot_from_kernel(machine, ppc405->soc.cpu); > + boot_from_kernel(machine, &ppc405->soc.cpu); > } > } > > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index 59612504bf3f..b84749b36114 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -1432,10 +1432,18 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], > #endif > } > > +static void ppc405_soc_instance_init(Object *obj) > +{ > + Ppc405SoCState *s = PPC405_SOC(obj); > + > + object_initialize_child(obj, "cpu", &s->cpu, > + POWERPC_CPU_TYPE_NAME("405ep")); > +} > + > static void ppc405_soc_realize(DeviceState *dev, Error **errp) > { > Ppc405SoCState *s = PPC405_SOC(dev); > - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; > + clk_setup_t clk_setup[PPC405EP_CLK_NB]; > qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; > CPUPPCState *env; > Error *err = NULL; > @@ -1462,12 +1470,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp) > memset(clk_setup, 0, sizeof(clk_setup)); > > /* init CPUs */ > - s->cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), > - &clk_setup[PPC405EP_CPU_CLK], > - &tlb_clk_setup, s->sysclk); > - env = &s->cpu->env; > - clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; > - clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; > + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { > + return; > + } > + > + env = &s->cpu.env; > + > + clk_setup[PPC405EP_CPU_CLK].cb = > + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT); > + clk_setup[PPC405EP_CPU_CLK].opaque = env; > + > + ppc_dcr_init(env, NULL, NULL); > > /* CPU control */ > ppc405ep_cpc_init(env, clk_setup, s->sysclk); > @@ -1484,16 +1497,16 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp) > /* Universal interrupt controller */ > s->uic = qdev_new(TYPE_PPC_UIC); > > - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu), > + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu), > &error_fatal); > if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) { > return; > } > > sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT, > - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT)); > + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)); > sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT, > - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT)); > + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT)); > > /* SDRAM controller */ > /* XXX 405EP has no ECC interrupt */ > @@ -1575,6 +1588,7 @@ static const TypeInfo ppc405_types[] = { > .name = TYPE_PPC405_SOC, > .parent = TYPE_DEVICE, > .instance_size = sizeof(Ppc405SoCState), > + .instance_init = ppc405_soc_instance_init, > .class_init = ppc405_soc_class_init, > } > };