From: Cezary Rojewski <cezary.rojewski@intel.com>
To: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
<alsa-devel@alsa-project.org>
Cc: upstream@semihalf.com, harshapriya.n@intel.com, rad@semihalf.com,
tiwai@suse.com, hdegoede@redhat.com, broonie@kernel.org,
ranjani.sridharan@linux.intel.com,
amadeuszx.slawinski@linux.intel.com, cujomalainey@chromium.org,
lma@semihalf.com
Subject: Re: [PATCH v4 04/17] ASoC: Intel: avs: Inter process communication
Date: Fri, 11 Mar 2022 16:40:00 +0100 [thread overview]
Message-ID: <9e495c5e-e8c1-8111-1526-3354e2cb59e1@intel.com> (raw)
In-Reply-To: <e0f4bc39-91e6-aead-a6c4-90251298d37d@linux.intel.com>
On 2022-03-09 11:10 PM, Pierre-Louis Bossart wrote:
>
>> +/*
>> + * struct avs_dsp_ops - Platform-specific DSP operations
>> + *
>> + * @power: Power on or off DSP cores
>> + * @reset: Enter or exit reset state on DSP cores
>> + * @stall: Stall or run DSP cores
>
> nit-pick: the description sounds like boolean states. add "callback to"
The title i.e. struct's description reads: *DSP operations*. And thus I
believe the *DSP operation* prefix applies to everything below
implicitly. Otherwise we have spam of: "A callback to do <this and that>".
>> + * @irq_handler: Top half of IPC servicing
>> + * @irq_thread: Bottom half of IPC servicing
>> + * @int_control: Enable or disable IPC interrupts
>
> callback to ...
Ditto.
>> + */
>> struct avs_dsp_ops {
>> int (* const power)(struct avs_dev *, u32, bool);
>> int (* const reset)(struct avs_dev *, u32, bool);
>> int (* const stall)(struct avs_dev *, u32, bool);
>> + irqreturn_t (* const irq_handler)(int, void *);
>> + irqreturn_t (* const irq_thread)(int, void *);
>> + void (* const int_control)(struct avs_dev *, bool);
>> };
>
>> +/*
>> + * struct avs_ipc - DSP IPC context
>> + *
>> + * @dev: PCI device
>> + * @rx: Reply message cache
>
> cache? I find this confusing, what are you trying to say here?
The goal of that member is to reduce amount of memory allocations needed
during message processing. That's why it's called cache.
>> + * @default_timeout_ms: default message timeout in MS
>> + * @ready: whether firmware is ready and communication is open
>> + * @rx_completed: whether RX for previously sent TX has been received
>> + * @rx_lock: for serializating manipulation of rx_* fields
>
> typo: serializing
Ack.
>> + * @msg_lock: for synchronizing request handling
>> + * @done_completion: DONE-part of IPC i.e. ROM and ACKs from FW
>> + * @busy_completion: BUSY-part of IPC i.e. receiving responses from FW
>> + */
>> +struct avs_ipc {
>> + struct device *dev;
>> +
>> + struct avs_ipc_msg rx;
>> + u32 default_timeout_ms;
>> + bool ready;
>> +
>> + bool rx_completed;
>> + spinlock_t rx_lock;
>> + struct mutex msg_mutex;
>> + struct completion done_completion;
>> + struct completion busy_completion;
>> +};
>> +
>> +#define AVS_EIPC EREMOTEIO
>
> I don't recall if I already mentioned this but I don't see the need for
> an intermediate redefinition of a Linux error code.
Hmm.. I've already explained that code makes use of this macro to
differentiate between IPC protocol errors and *other* errors. Otherwise,
if code gets changed, every single usage -EREMOTEIO will need to be
addressed, not just AVS_EIPC declaration.
>> +/*
>> + * IPC handlers may return positive value (firmware error code) what
>> denotes
>> + * successful HOST <-> DSP communication yet failure to process
>> specific request.
>> + *
>> + * Below macro converts returned value to linux kernel error code.
>> + * All IPC callers MUST use it as soon as firmware error code is
>> consumed.
>> + */
>> +#define AVS_IPC_RET(ret) \
>> + (((ret) <= 0) ? (ret) : -AVS_EIPC)
>> +
>> +static inline void avs_ipc_err(struct avs_dev *adev, struct
>> avs_ipc_msg *tx,
>> + const char *name, int error)
>> +{
>> + /*
>> + * If IPC channel is blocked e.g.: due to ongoing recovery,
>> + * -EPERM error code is expected and thus it's not an actual error.
>> + */
>> + if (error == -EPERM)
>> + dev_dbg(adev->dev, "%s 0x%08x 0x%08x failed: %d\n", name,
>
> %# adds the 0x for you.
>
>> + tx->glb.primary, tx->glb.ext.val, error);
>> + else
>> + dev_err(adev->dev, "%s 0x%08x 0x%08x failed: %d\n", name,
>> + tx->glb.primary, tx->glb.ext.val, error);
>> +}
>
>> +static void avs_dsp_process_notification(struct avs_dev *adev, u64
>> header)
>> +{
>> + struct avs_notify_mod_data mod_data;
>> + union avs_notify_msg msg = AVS_MSG(header);
>> + size_t data_size = 0;
>> + void *data = NULL;
>> +
>> + /* Ignore spurious notifications until handshake is established. */
>
> there's no handshake here, just an initial notification after which the
> IPC protocol can start?
There is no *real* handshake yes, but the FW_READY is sent as a response
to us (the driver) programming ADSP cores and loading firmware.
Regards,
Czarek
next prev parent reply other threads:[~2022-03-11 15:41 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 20:40 [PATCH v4 00/17] ASoC: Intel: AVS - Audio DSP for cAVS Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 01/17] ALSA: hda: Add helper macros for DSP capable devices Cezary Rojewski
2022-03-10 13:30 ` Takashi Iwai
2022-03-09 20:40 ` [PATCH v4 02/17] ASoC: Export DAI register and widget ctor and dctor functions Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 03/17] ASoC: Intel: Introduce AVS driver Cezary Rojewski
2022-03-09 21:58 ` Pierre-Louis Bossart
2022-03-11 15:32 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 04/17] ASoC: Intel: avs: Inter process communication Cezary Rojewski
2022-03-09 22:10 ` Pierre-Louis Bossart
2022-03-11 15:40 ` Cezary Rojewski [this message]
2022-03-09 20:40 ` [PATCH v4 05/17] ASoC: Intel: avs: Add code loading requests Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 06/17] ASoC: Intel: avs: Add pipeline management requests Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 07/17] ASoC: Intel: avs: Add module " Cezary Rojewski
2022-03-09 22:16 ` Pierre-Louis Bossart
2022-03-11 15:40 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 08/17] ASoC: Intel: avs: Add power " Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 09/17] ASoC: Intel: avs: Add ROM requests Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 10/17] ASoC: Intel: avs: Add basefw runtime-parameter requests Cezary Rojewski
2022-03-09 22:20 ` Pierre-Louis Bossart
2022-03-09 20:40 ` [PATCH v4 11/17] ASoC: Intel: avs: Firmware resources management utilities Cezary Rojewski
2022-03-09 22:36 ` Pierre-Louis Bossart
2022-03-10 17:11 ` Cezary Rojewski
2022-03-11 12:10 ` Mark Brown
2022-03-11 15:28 ` Cezary Rojewski
2022-03-11 15:46 ` Cezary Rojewski
2022-03-11 15:59 ` Pierre-Louis Bossart
2022-03-11 17:20 ` Cezary Rojewski
2022-03-11 20:30 ` Pierre-Louis Bossart
2022-03-14 17:59 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 12/17] ASoC: Intel: avs: Declare module configuration types Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 13/17] ASoC: Intel: avs: Dynamic firmware resources management Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 14/17] ASoC: Intel: avs: General code loading flow Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 15/17] ASoC: Intel: avs: Implement CLDMA transfer Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 16/17] ASoC: Intel: avs: Code loading over CLDMA Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 17/17] ASoC: Intel: avs: Code loading over HDA Cezary Rojewski
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