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Mon, 21 Sep 2026 08:56:59 -0700 (PDT) Message-ID: <9ea9edfc-be76-4507-8b71-a483daa9e7d5@suse.com> Date: Mon, 21 Sep 2026 17:57:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] xen/riscv: make Svpbmt no longer a required extension To: Baptiste Le Duc Cc: xen-devel@lists.xenproject.org, Alistair Francis , Connor Davis , Oleksii Kurochko , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <1789032657.8631fc262581453bbf619ec5b2062170.1a08aa7f23b000c4f3@vates.tech> <1789032898.8631fc262581453bbf619ec5b2062170.1a08aab9fe1000c4f3@vates.tech> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1789032898.8631fc262581453bbf619ec5b2062170.1a08aab9fe1000c4f3@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1790006219-CF95A87B-E12904DB/0/0 X-purgate-type: clean X-purgate-size: 4312 On 10.09.2026 11:34, Baptiste Le Duc wrote: > Without the Svpbmt extension, memory attributes (such as cacheability and > ordering) are strictly tied to physical address ranges and enforced by the > hardware's Physical Memory Attributes (PMA) checker. > > In this configuration, supervisor software relies on the platform's memory > map: > - peripheral device registers (MMIO) are physically mapped into > hardware-defined I/O regions (which are implicitly non-cacheable and > strongly-ordered) > - regular RAM is mapped as cacheable main memory. > > S-mode paging can safely map these physical ranges without specifying > page-based memory types in the PTEs, as the hardware MMU and PMA pipeline > will correctly bypass caches for MMIO accesses and use caches for RAM > accesses, based on the target physical address. Provided firmware got absolutely everything right. > Furthermore, on platforms that either feature fully hardware-coherent DMA > or don't expose non-coherent DMA agents to the OS, page-level programmatic > cache control via Svpbmt is not required, making it safe to boot and run > when Svpbmt is absent. Yet a fully coherent platform should also be possible to somehow identify? > Drop Svpbmt from required_extensions. Introduce svpbmt_enabled, a > __ro_after_init flag computed once in init_csr_masks() from ISA > availability and the henvcfg.PBMTE bit. Xen cannot read menvcfg.PBMTE > directly, since menvcfg is M-mode-only and unreadable from HS-mode, but the > spec guarantees henvcfg.PBMTE reads as zero whenever menvcfg.PBMTE is zero, > so checking henvcfg.PBMTE alone is sufficient. I don't understand this logic. If menvcfg.PBMTE is non-zero, we know nothing about (or from) henvcfg.PBMTE's setting. > --- a/xen/arch/riscv/domain.c > +++ b/xen/arch/riscv/domain.c > @@ -47,6 +47,8 @@ static struct csr_masks __ro_after_init csr_masks; > #define HENVCFG_VALID_MASK 0xe0000003000000ffUL > #define HSTATEEN0_VALID_MASK 0xde00000000000007UL > > +bool __ro_after_init svpbmt_enabled; > + > void __init init_csr_masks(void) > { > /* > @@ -79,6 +81,10 @@ void __init init_csr_masks(void) > INIT_RO_ONE_MASK(HSTATEEN0, hstateen0); > } > > + svpbmt_enabled = (riscv_isa_extension_available(NULL, > + RISCV_ISA_EXT_svpbmt)) && (ENVCFG_PBMTE & > + csr_masks.henvcfg); Line wrapping wants doing entirely differently here. One of the style- conforming options is svpbmt_enabled = riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) && (csr_masks.henvcfg & ENVCFG_PBMTE); > --- a/xen/arch/riscv/include/asm/page.h > +++ b/xen/arch/riscv/include/asm/page.h > @@ -11,6 +11,7 @@ > #include > > #include > +#include > #include > > #define VPN_MASK (PAGETABLE_ENTRIES - 1UL) > @@ -42,7 +43,21 @@ > * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory > * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory > * 11 - Rsvd Reserved for future standard use > + * > + * These bits are only meaningful when Svpbmt is enabled. Otherwise they must > + * stay 0 (PMA). > */ > +extern bool svpbmt_enabled; > +static inline unsigned long pte_pbmt_nocache(void) > +{ > + return svpbmt_enabled ? BIT(61, UL) : 0; > +} > + > +static inline unsigned long pte_pbmt_io(void) > +{ > + return svpbmt_enabled ? BIT(62, UL) : 0; > +} Why open-code ... > #define PTE_PBMT_NOCACHE BIT(61, UL) > #define PTE_PBMT_IO BIT(62, UL) ... what is still available here? > @@ -53,6 +68,7 @@ > #define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUTABLE | PTE_ACCESSED) > > #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW > + > /* > * PAGE_HYPERVISOR_NOCACHE is used for ioremap(). > * Stray change? > @@ -82,7 +98,7 @@ enum pbmt_type { > > #define PTE_ACCESS_MASK (PTE_READABLE | PTE_WRITABLE | PTE_EXECUTABLE) > > -#define PTE_PBMT_MASK (PTE_PBMT_NOCACHE | PTE_PBMT_IO) > +#define PTE_PBMT_MASK (BIT(61, UL) | BIT(62, UL)) I don't understand the need for this change. Jan