Re: [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC

[Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>]

On 2020-11-30 15:09, Manivannan Sadhasivam wrote:
> SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN 
> register
> needs to be written to enable the Write Sub Cache for each SCID. Hence,
> use a dedicated "write_scid_en" member with predefined values and write
> them for LLCC IP version 2.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

>  drivers/soc/qcom/llcc-qcom.c       | 38 ++++++++++++++++++++++++++++++
>  include/linux/soc/qcom/llcc-qcom.h |  1 +
>  2 files changed, 39 insertions(+)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c 
> b/drivers/soc/qcom/llcc-qcom.c
> index a559617ea7c0..8403a77b59fe 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -51,6 +51,7 @@
> 
>  #define LLCC_TRP_SCID_DIS_CAP_ALLOC   0x21f00
>  #define LLCC_TRP_PCB_ACT              0x21f04
> +#define LLCC_TRP_WRSC_EN              0x21f20
> 
>  #define BANK_OFFSET_STRIDE	      0x80000
> 
> @@ -77,6 +78,7 @@
>   *               then the ways assigned to this client are not flushed 
> on power
>   *               collapse.
>   * @activate_on_init: Activate the slice immediately after it is 
> programmed
> + * @write_scid_en: Bit enables write cache support for a given scid.
>   */
>  struct llcc_slice_config {
>  	u32 usecase_id;
> @@ -91,6 +93,7 @@ struct llcc_slice_config {
>  	bool dis_cap_alloc;
>  	bool retain_on_pc;
>  	bool activate_on_init;
> +	bool write_scid_en;
>  };
> 
>  struct qcom_llcc_config {
> @@ -151,6 +154,25 @@ static const struct llcc_slice_config 
> sm8150_data[] =  {
>  	{  LLCC_WRCACHE, 31, 128,  1, 1, 0xFFF, 0x0,   0, 0, 0, 0, 0 },
>  };
> 
> +static const struct llcc_slice_config sm8250_data[] =  {
> +	{ LLCC_CPUSS,    1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
> +	{ LLCC_VIDSC0,   2, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_AUDIO,    6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
> +	{ LLCC_CMPT,    10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
> +	{ LLCC_GPUHTW,  11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_GPU,     12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
> +	{ LLCC_MMUHWT,  13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> +	{ LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_DISP,    16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_VIDFW,   17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_AUDHW,   22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_NPU,     23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_WLHW,    24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_CVP,     28, 256,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_APTCM,   30, 128,  3, 0, 0x0,   0x3, 1, 0, 0, 1, 0, 0 },
> +	{ LLCC_WRCACHE, 31, 256,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> +};
> +
>  static const struct qcom_llcc_config sc7180_cfg = {
>  	.sct_data	= sc7180_data,
>  	.size		= ARRAY_SIZE(sc7180_data),
> @@ -168,6 +190,11 @@ static const struct qcom_llcc_config sm8150_cfg = 
> {
>  	.size           = ARRAY_SIZE(sm8150_data),
>  };
> 
> +static const struct qcom_llcc_config sm8250_cfg = {
> +	.sct_data       = sm8250_data,
> +	.size           = ARRAY_SIZE(sm8250_data),
> +};
> +
>  static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
> 
>  /**
> @@ -417,6 +444,16 @@ static int _qcom_llcc_cfg_program(const struct
> llcc_slice_config *config,
>  			return ret;
>  	}
> 
> +	if (drv_data->major_version == 2) {
> +		u32 wren;
> +
> +		wren = config->write_scid_en << config->slice_id;
> +		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
> +					 BIT(config->slice_id), wren);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	if (config->activate_on_init) {
>  		desc.slice_id = config->slice_id;
>  		ret = llcc_slice_activate(&desc);
> @@ -571,6 +608,7 @@ static const struct of_device_id 
> qcom_llcc_of_match[] = {
>  	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
>  	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
>  	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
> +	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
>  	{ }
>  };
> 
> diff --git a/include/linux/soc/qcom/llcc-qcom.h
> b/include/linux/soc/qcom/llcc-qcom.h
> index d17a3de80510..64fc582ae415 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -29,6 +29,7 @@
>  #define LLCC_AUDHW       22
>  #define LLCC_NPU         23
>  #define LLCC_WLHW        24
> +#define LLCC_CVP         28
>  #define LLCC_MODPE       29
>  #define LLCC_APTCM       30
>  #define LLCC_WRCACHE     31

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