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[78.54.176.138]) by smtp.gmail.com with ESMTPSA id t20-20020a0560001a5400b002c54f4d0f71sm6897477wry.38.2023.03.04.23.34.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 04 Mar 2023 23:34:23 -0800 (PST) Date: Sun, 05 Mar 2023 07:34:15 +0000 From: Bernhard Beschow To: BALATON Zoltan , qemu-devel@nongnu.org, qemu-ppc@nongnu.org CC: Gerd Hoffmann , Daniel Henrique Barboza , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Subject: Re: [PATCH v6 3/7] hw/isa/vt82c686: Implement PCI IRQ routing In-Reply-To: <7c2b8906bc5fc9ac5eb8836ca2f6dc05c9046c01.1677940224.git.balaton@eik.bme.hu> References: <7c2b8906bc5fc9ac5eb8836ca2f6dc05c9046c01.1677940224.git.balaton@eik.bme.hu> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=shentey@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 4=2E M=C3=A4rz 2023 14:48:20 UTC schrieb BALATON Zoltan : >The real VIA south bridges implement a PCI IRQ router which is configured >by the BIOS or the OS=2E In order to respect these configurations, QEMU >needs to implement it as well=2E The real chip may allow routing IRQs fro= m >internal functions independently of PCI interrupts but since guests >usually configute it to a single shared interrupt we don't model that >here for simplicity=2E > >Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4= =2E > >Suggested-by: Bernhard Beschow >Signed-off-by: BALATON Zoltan >Tested-by: Rene Engel >--- > hw/isa/vt82c686=2Ec | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > >diff --git a/hw/isa/vt82c686=2Ec b/hw/isa/vt82c686=2Ec >index f4c40965cd=2E=2E51c0dd4c41 100644 >--- a/hw/isa/vt82c686=2Ec >+++ b/hw/isa/vt82c686=2Ec >@@ -598,6 +598,42 @@ void via_isa_set_irq(PCIDevice *d, int n, int level) > qemu_set_irq(s->isa_irqs_in[n], level); > } >=20 >+static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) >+{ >+ switch (irq_num) { >+ case 0: >+ return s->dev=2Econfig[0x55] >> 4; >+ case 1: >+ return s->dev=2Econfig[0x56] & 0xf; >+ case 2: >+ return s->dev=2Econfig[0x56] >> 4; >+ case 3: >+ return s->dev=2Econfig[0x57] >> 4; >+ } >+ return 0; >+} >+ >+static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) >+{ >+ ViaISAState *s =3D opaque; >+ PCIBus *bus =3D pci_get_bus(&s->dev); >+ int i, pic_level, pic_irq =3D via_isa_get_pci_irq(s, irq_num); >+ >+ if (unlikely(pic_irq =3D=3D 0 || pic_irq =3D=3D 2 || pic_irq > 14)) = { In the previous iteration I already mentioned this: Why "pic_irq > 14"? Pl= ease either remove or put a comment in the code since the datasheet allows = it=2E Otherwise this leads to hard to comprehend and therefore hard to main= tain code=2E Moreover, "pic_irq =3D=3D 2" is reserved which we should log a guest error= for=2E Otherwise, misbehaving guests will go unnoticed, which is exactly w= hat guest errors should prevent=2E Also, logging a guest error here makes t= he code more self documenting=2E Note that excess logging can always be filtered out using grep=2E Best regards, Bernhard >+ return; >+ } >+ >+ /* The pic level is the logical OR of all the PCI irqs mapped to it= =2E */ >+ pic_level =3D 0; >+ for (i =3D 0; i < PCI_NUM_PINS; i++) { >+ if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { >+ pic_level |=3D pci_bus_get_irq_level(bus, i); >+ } >+ } >+ /* Now we change the pic irq level according to the via irq mappings= =2E */ >+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); >+} >+ > static void via_isa_realize(PCIDevice *d, Error **errp) > { > ViaISAState *s =3D VIA_ISA(d); >@@ -619,6 +655,8 @@ static void via_isa_realize(PCIDevice *d, Error **err= p) > i8254_pit_init(isa_bus, 0x40, 0, NULL); > i8257_dma_init(isa_bus, 0); >=20 >+ qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PI= NS); >+ > /* RTC */ > qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); > if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {