From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keir Fraser Subject: Re: [PATCH 0/3][IA64] Accelerate IDE PIO on HVM/IA64 Date: Tue, 27 Feb 2007 10:56:16 +0000 Message-ID: References: <200702270850.l1R8oeK3019985@bx604.sky.yk.fujitsu.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <200702270850.l1R8oeK3019985@bx604.sky.yk.fujitsu.co.jp> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Kouya SHIMURA , Alex Williamson Cc: xen-devel@lists.xensource.com, xen-ia64-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org On 27/2/07 09:34, "Kouya SHIMURA" wrote: > The basic idea is to add a buffering mechanism in a hypervisor. > I know this approach is not sophisticated. But there is no other > good way in IA64 which has no string instructions like x86's. > > This patchset is indispensable to support windows/ia64 on HVM > since installing windows and crash dumping is terribly slow. Can you explain how this new code works? As I understand it the problem is that each PIO instruction decoded by Xen and propagated to qemu only transfers a single word of data. How does this new buffering mechanism work around this? -- Keir