Re: NMI deferral on i386

[Keir Fraser <keir@xensource.com>]

On 15/5/07 15:46, "Jan Beulich" <jbeulich@novell.com> wrote:

> - by using iret, the NMI is being acknowledged to the CPU, and since nothing
>   was done to address its reason, I can't see why it shouldn't re-trigger
>   right after that iret (unless it was sent as an IPI)

Yes, it's good enough for watchdog and oprofile. Level-triggered external
NMIs will of course be a problem. We could possibly work around this by
masking LINT1 if we are CPU0 (and, of course, if LAPIC is enabled) and then
unmasking only at the end of real NMI handler. And of course x86/64 doesn't
have this problem at all, and practically speaking is pretty much the only
hypervisor build that vendors seem to care about.

> - by re-issuing it on vector 31, the resulting interrupt will have lower
> priority
>   than any external interrupt, hence all pending interrupts will be serviced
>   before getting to actually handle the NMI; ideally this should use the
> highest
>   possible vector, but since priorities are grouped anyway, at least
> allocating
>   the vector from the high priority pool would seem necessary

Yes, this is true.

 -- Keir