From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keir Fraser Subject: Re: [VTD][patch 0/5] HVM device assignment using vt-d Date: Thu, 31 May 2007 14:37:18 +0100 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "Tian, Kevin" , Guy Zana , "Kay, Allen M" , xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org On 31/5/07 14:20, "Tian, Kevin" wrote: > When driver requests device to clear interrupt assertion at end > of handling 1st, it's possible that device keeps assertion if interrupt > condition still matches in 2nd. In that case, no interrupt will happen > any more when EOI is written to IOAPIC due to polarity inversion. This is absolutely fine. The virtual wire status will remain HIGH in this case, which is correct since the 'runt' LOW pulse on the physical wire can be ignored. What we are looking for is to track the physical wire status in the long run; pulses one way or the other do not matter. Remember we are talking about *level-triggered* interrupt lines, not edge-triggered. This polarity-change trick would not be used, and would not be necessary, for edge-triggered interrupts. We would EOI the physical APIC early, before running the ISR, just as usual for edge-triggered interrupts. Because we are talking about level-triggered interrupts, if the line continues to be HIGH after the ISR runs then of course we'll just deliver another interrupt straight to the relevant VCPU. That's how level-triggered interrupts work. :-) -- Keir