From: Keir Fraser <keir@xensource.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: xen-devel@lists.xensource.com
Subject: Re: [PATCH 6/10] Allow vcpu to pause self
Date: Thu, 12 Jul 2007 08:44:56 +0100 [thread overview]
Message-ID: <C2BB9A88.AB08%keir@xensource.com> (raw)
In-Reply-To: <D470B4E54465E3469E2ABBC5AFAC390F013B1FCC@pdsmsx412.ccr.corp.intel.com>
On 12/7/07 06:05, "Tian, Kevin" <kevin.tian@intel.com> wrote:
>> But after a further thinking, based on the fact that enter_state will force
>> a lazy context flush on all CPUs now, this interface can be abandoned
>> then.
>>
>
> Seems issue still existing. It's possible that force lazy context flush
> in enter_state is done before dom0/vcpu0 enters context switch,
> since softirq is sent out before pause. How to find a safe point where
> we know that dom0/vcpu0 is definitely switched out?
How about doing the whole suspend/resume in dom0/vcpu0 context? Why switch
to a softirq at all? You can force dom0/vcpu0 onto cpu0 temporarily by
wrapping the suspend/resume in a pair of calls to vcpu_set_affinity().
If your register save/restore across the low-level S3 entry/exit is
comprehensive, then it should be fine to do it in dom0/vcpu0 context.
-- Keir
next prev parent reply other threads:[~2007-07-12 7:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-27 13:37 [PATCH 6/10] Allow vcpu to pause self Tian, Kevin
2007-07-11 17:02 ` Keir Fraser
2007-07-12 2:37 ` Tian, Kevin
2007-07-12 5:05 ` Tian, Kevin
2007-07-12 6:02 ` Tian, Kevin
2007-07-12 7:41 ` Keir Fraser
2007-07-12 8:07 ` Tian, Kevin
2007-07-12 7:44 ` Keir Fraser [this message]
2007-07-12 8:01 ` Keir Fraser
2007-07-12 8:23 ` Tian, Kevin
2007-07-12 8:30 ` Keir Fraser
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