Re: Buffered IO for IO?

[Keir Fraser <keir@xensource.com>]

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Yes, it strikes me that this cannot be done safely without providing a set
of Œproxy device models¹ in the hypervisor that know when it is safe to
buffer and when the buffers must be flushed, according to native hardware
behaviour.

 -- Keir

On 21/7/07 11:59, "Trolle Selander" <trolle.selander@gmail.com> wrote:

> Safety would depend on how the emulated device works. For serial ports in
> particular, it's definitely not safe, since depending on the model of UART
> emulated, and the settings of the UART control registers, every outb may
> result in a serial interrupt and UART register changes that will have to be
> processed before any further io can be done.
> It's possible that there might be some performance to be gained by "upgrading"
> the emulated UART to a 16550A or better, and doing buffered IO for the FIFO.
> Earlier this year I was experimenting with a patch that made the qemu-dm
> serial emulation into a 16550A with FIFO, but though the patch did fix some
> compatability issues with software that assumed a 16550A UART in the HVM guest
> I'm working with, serial performance actually got noticeably _worse_, so I
> never bothered submitting it. Implementing the FIFO with buffered IO would
> possibly make it work better, but I don't see how it could be done without
> moving at least part of the serial device model into the hypervisor, which
> just strikes me as more trouble than it's worth.
> 
> /Trolle
> 
> On 7/21/07, Keir Fraser <keir@xensource.com> wrote:
>> 
>> 
>> 
>> On 20/7/07 22:33, "Zulauf, John" <john.zulauf@intel.com> wrote:
>> 
>>> > Has anyone experimented with adding Buffered IO support for "out"
>>> > instructions?  Currently, the buffered io pages is only used for mmio
>>> > writes (and then only to vga space).  It seems quite straight-forward to
>>> > add.
>> 
>> Is it safe to buffer, and hence arbitrarily delay, any I/O port write?
>> 
>>  -- Keir
>> 
>> 
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> 
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