From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keir Fraser <keir@xensource.com>
Subject: Re: NMI delivery not correctly working
Date: Wed, 25 Jul 2007 07:55:11 +0100
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References: <0EF82802ABAA22479BC1CE8E2F60E8C3017E79E5@scl-exch2k3.phoenix.com>
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To: Kaushik Barde <Kaushik_Barde@Phoenix.com>, Christoph Egger <Christoph.Egger@amd.com>, xen-devel@lists.xensource.com
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On 25/7/07 07:43, "Kaushik Barde" <Kaushik_Barde@Phoenix.com> wrote:

> Thanks. 
>  
>>> 
> via masking of maskable interrupts
> <<
> What I'd meant there was all other interrupts are masked (by processor during
> NMI handling) except for NMI.

NMIs *are* masked by x86 CPU from when an NMI is delivered to the CPU until
after that CPU next executes an IRET. The CPU has a special NMI mask for
this purpose (not directly architecturally visible). It's unrelated to
EFLAGS.IF.

 -- Keir