From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keir Fraser <keir.fraser@eu.citrix.com>
Subject: Re: [Patch] x86: enforce strict memory order for x2apic
Date: Thu, 25 Sep 2008 09:36:19 +0100
Message-ID: <C5010C13.27732%keir.fraser@eu.citrix.com>
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To: "Tian, Kevin" <kevin.tian@intel.com>, 'Jan Beulich' <jbeulich@novell.com>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
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On 25/9/08 09:29, "Tian, Kevin" <kevin.tian@intel.com> wrote:

>> On the other hand you're penalizing LAPIC systems with this, too. I'm
>> not certain that's better than fixing the (incorrect)
>> assumptions just in
>> the x2APIC case.
> 
> I agree. I'll revise the patch to add a 'mb()' in x2APIC instead,
> though that may bring a bit overhead to cases when fencing
> is not required, like event check IPI.

To be precise, mb() at top of send_IPI_mask_x2apic(), and wmb() may as well
go from on_selected_cpus() as we can assume send_IPI_mask() is a barrier.

I'll do the patch for this myself.

 -- Keir