From mboxrd@z Thu Jan  1 00:00:00 1970
From: Scott Feldman <sfeldma@nuovasystems.com>
Subject: Re: drivers/net/enic/vnic_cq.c
Date: Fri, 10 Oct 2008 11:29:23 -0700
Message-ID: <C514ED13.C7D0%sfeldma@nuovasystems.com>
References: <adaabdcjrz8.fsf@cisco.com>
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Cc: <akpm@linux-foundation.org>, <mingo@elte.hu>,
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To: Roland Dreier <rdreier@cisco.com>,
	David Miller <davem@davemloft.net>
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On 10/10/08 10:10 AM, "Roland Dreier" <rdreier@cisco.com> wrote:

> cc'ing Scott so we can make sure that this actually is atomic enough to
> work with the enic hardware... (Scott, the context is that enic won't
> build on any architecture that doesn't define writeq and readq, such as
> 32-bit x86; however the definitions below make it possible that multiple
> 32-bit writes will be interleaved, eg if an interrupt occurs between the
> first writel and the second writel)

Yes, enic hw provides atomic read/write for 64-bit regs even if register is
accessed with 32-bit read/writes.

-scott