From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keir Fraser Subject: Re: [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0. Date: Fri, 03 Jul 2009 10:33:19 +0100 Message-ID: References: <7kzlbmmc69.fsf@pingu.sky.yk.fujitsu.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <7kzlbmmc69.fsf@pingu.sky.yk.fujitsu.co.jp> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Kouya Shimura Cc: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org On 03/07/2009 08:57, "Kouya Shimura" wrote: > - I'm afraid that d->arch.hvm_domain.i8259_target == NULL If VCPUj is != NULL then VCPUi is also != NULL for all i < j. So this is not a concern: there's always a VCPU0 if there are any VCPUs at all. > - if vcpu[0] is halted and all vlapic.LVT0 are masked, > timer doesn't work even when vlapic will be unmasked > not as ExtINT mode. Not sure what you mean? If legacy IRQs are routed through the IOAPIC then it does not matter whether LAPIC.LVT0 is masked. And __vlapic_accept_pic_intr() correctly handles that. If virtual wire mode is not through the IOAPIC then of course LVT0 mask does matter, but I think we have that case correct too. > So, I think that the last __vlapic_accept_pic_intr'ed vcpu > should be reserved in d->arch.hvm_domain.i8259_target. I don't think the logic needs to change. -- Keir