From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keir Fraser Subject: Re: [PATCH 4/4] amd iommu: Large io page support - implementation Date: Tue, 07 Dec 2010 18:00:45 +0000 Message-ID: References: <201012071220.03624.wei.wang2@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <201012071220.03624.wei.wang2@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Wei Wang2 , "Kay, Allen M" Cc: Tim Deegan , "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org Cc'ing Tim -- he could advise how plausible it is to find other available bits to move the p2m types to. Also I'm not sure whether the p2m tables eve= r get used as host pagetables these days (e.g., when guest has CR0.PG=3D0). Tha= t could affect how difficult it is to mess with the p2m format. If it's possible, though, it's probably worth pursuing. Sharing the tables uses less memory, and could be less complicated code too. -- Keir On 07/12/2010 11:20, "Wei Wang2" wrote: > Hi Allen, > Actually, each amd iommu pde entry uses bit 9-11 to encode next page tabl= e > level, but these bits are also used as AVL bits by p2m table to encode > different page types...So, it might not be quite easy to share NPT table = with > amd iommu unless we change p2m table encoding for this first. > Thanks, > Wei >=20 > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote: >> Hi Wei, >>=20 >> My understanding is that both EPT/NPT already supports 2M and 1G page >> sizes. If this is true and if NPT supports the same page table format a= s >> AMD iommu, shouldn't iommu 2M and 1G support just a matter of pointing >> iommu page table pointer to NPT page table of the same guest OS thus >> sharing the same page table between NPT and AMD iommu? >>=20 >> This should save a lot code changes in iommu code. We just need to flus= h >> iommu page table in IOTLB at appropriate places. >>=20 >> Allen >>=20 >> -----Original Message----- >> From: xen-devel-bounces@lists.xensource.com >> [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 Se= nt: >> Friday, December 03, 2010 8:04 AM >> To: xen-devel@lists.xensource.com >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - >> implementation >>=20 >> This is the implementation. >>=20 >> Thanks, >> We >> Signed-off-by: Wei Wang >> -- >> Legal Information: >> Advanced Micro Devices GmbH >> Sitz: Dornach, Gemeinde Aschheim, >> Landkreis M=FCnchen Registergericht M=FCnchen, HRB Nr. 43632 >> Gesch=E4ftsf=FChrer: >> Alberto Bozzo, Andrew Bowd >=20 >=20 >=20 >=20 > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel