From: Keir Fraser <keir.xen@gmail.com>
To: Wei Huang <wei.huang2@amd.com>,
"'xen-devel@lists.xensource.com'" <xen-devel@lists.xensource.com>
Subject: Re: [PATCH][RFC] FPU LWP 0/5: patch description
Date: Thu, 14 Apr 2011 22:09:59 +0100 [thread overview]
Message-ID: <C9CD2137.16600%keir.xen@gmail.com> (raw)
In-Reply-To: <4DA75B07.6010503@amd.com>
On 14/04/2011 21:37, "Wei Huang" <wei.huang2@amd.com> wrote:
> The following patches support AMD lightweight profiling.
>
> Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to
> handle lazy and unlazy FPU states differently. Lazy FPU state (such as
> SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP,
> is saved and restored on each vcpu context switch. To simplify the code,
> we also add a mask option to xsave/xrstor function.
How much cost is added to context switch paths in the (overwhelmingly
likely) case that LWP is not being used by the guest? Is this adding a whole
lot of unconditional overhead for a feature that noone uses?
-- Keir
> Thanks,
> -Wei
>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
next prev parent reply other threads:[~2011-04-14 21:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-14 20:37 [PATCH][RFC] FPU LWP 0/5: patch description Wei Huang
2011-04-14 21:09 ` Keir Fraser [this message]
2011-04-14 22:57 ` Wei Huang
2011-04-15 20:16 ` Dan Magenheimer
2011-04-15 20:23 ` Huang2, Wei
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